// Verilog netlist produced by program LSE :  version Diamond (64-bit) 3.10.3.144
// Netlist written on Wed Sep 14 11:03:44 2022
//
// Verilog Description of module top
//

module top (clk, led, pwm, tx, rx) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(1[8:11])
    input clk;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    output led;   // f:/home/mini-step-fpga/prj/template/top.v(5[9:12])
    output pwm;   // f:/home/mini-step-fpga/prj/template/top.v(7[9:12])
    output tx;   // f:/home/mini-step-fpga/prj/template/top.v(9[9:11])
    input rx;   // f:/home/mini-step-fpga/prj/template/top.v(10[8:10])
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    
    wire GND_net, VCC_net, led_c, tx_c, rx_c, rst_n;
    wire [7:0]cmd;   // f:/home/mini-step-fpga/prj/template/top.v(17[19:22])
    
    wire wr;
    wire [31:0]wr_data;   // f:/home/mini-step-fpga/prj/template/top.v(19[12:19])
    wire [31:0]cmd_data;   // f:/home/mini-step-fpga/prj/template/top.v(20[13:21])
    
    wire valid_o;
    wire [2:0]led_status;   // f:/home/mini-step-fpga/prj/template/top.v(24[11:21])
    
    wire n509, n508, n507, n506, n505, n504, n503, n502, n501, 
        n500, n499, n498, n497, n496, n495, n494, n493, n492, 
        n491, n490, n489, n488, n487, n486, n485, n484, n483, 
        n482, n481, n480, n479, n478, n15, n13, n3702, n3701, 
        n3461, n3455, n3971, clk_c_enable_102, clk_c_enable_157;
    
    FD1P3IX led_status__i0 (.D(cmd_data[0]), .SP(clk_c_enable_157), .CD(n3702), 
            .CK(clk_c), .Q(led_status[0]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam led_status__i0.GSR = "DISABLED";
    LUT4 i2885_2_lut_rep_52 (.A(cmd[3]), .B(cmd[1]), .Z(n3701)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2885_2_lut_rep_52.init = 16'heeee;
    IB rx_pad (.I(rx), .O(rx_c));   // f:/home/mini-step-fpga/prj/template/top.v(10[8:10])
    FD1P3IX wr_data__i0 (.D(n509), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[0]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i0.GSR = "DISABLED";
    IB clk_pad (.I(clk), .O(clk_c));   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    LUT4 i2928_3_lut_4_lut (.A(cmd[3]), .B(cmd[1]), .C(n3455), .D(cmd[7]), 
         .Z(n3461)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2928_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2036_2_lut (.A(cmd_data[16]), .B(n15), .Z(n493)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2036_2_lut.init = 16'h8888;
    OB tx_pad (.I(tx_c), .O(tx));   // f:/home/mini-step-fpga/prj/template/top.v(9[9:11])
    OB pwm_pad (.I(GND_net), .O(pwm));   // f:/home/mini-step-fpga/prj/template/top.v(7[9:12])
    LUT4 i2035_2_lut (.A(cmd_data[15]), .B(n15), .Z(n494)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2035_2_lut.init = 16'h8888;
    FD1P3IX wr_data__i31 (.D(n478), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[31]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i31.GSR = "DISABLED";
    FD1P3IX wr_data__i30 (.D(n479), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[30]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i30.GSR = "DISABLED";
    FD1P3IX wr_data__i29 (.D(n480), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[29]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i29.GSR = "DISABLED";
    FD1P3IX wr_data__i28 (.D(n481), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[28]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i28.GSR = "DISABLED";
    FD1P3IX wr_data__i27 (.D(n482), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[27]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i27.GSR = "DISABLED";
    FD1P3IX wr_data__i26 (.D(n483), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[26]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i26.GSR = "DISABLED";
    FD1P3IX wr_data__i25 (.D(n484), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[25]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i25.GSR = "DISABLED";
    FD1P3IX wr_data__i24 (.D(n485), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[24]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i24.GSR = "DISABLED";
    FD1P3IX wr_data__i23 (.D(n486), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[23]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i23.GSR = "DISABLED";
    FD1P3IX wr_data__i22 (.D(n487), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[22]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i22.GSR = "DISABLED";
    FD1P3IX wr_data__i21 (.D(n488), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[21]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i21.GSR = "DISABLED";
    FD1P3IX wr_data__i20 (.D(n489), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[20]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i20.GSR = "DISABLED";
    FD1P3IX wr_data__i19 (.D(n490), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[19]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i19.GSR = "DISABLED";
    FD1P3IX wr_data__i18 (.D(n491), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[18]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i18.GSR = "DISABLED";
    FD1P3IX wr_data__i17 (.D(n492), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[17]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i17.GSR = "DISABLED";
    FD1P3IX wr_data__i16 (.D(n493), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[16]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i16.GSR = "DISABLED";
    FD1P3IX wr_data__i15 (.D(n494), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[15]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i15.GSR = "DISABLED";
    FD1P3IX wr_data__i14 (.D(n495), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[14]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i14.GSR = "DISABLED";
    FD1P3IX wr_data__i13 (.D(n496), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[13]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i13.GSR = "DISABLED";
    FD1P3IX wr_data__i12 (.D(n497), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[12]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i12.GSR = "DISABLED";
    FD1P3IX wr_data__i11 (.D(n498), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[11]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i11.GSR = "DISABLED";
    FD1P3IX wr_data__i10 (.D(n499), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[10]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i10.GSR = "DISABLED";
    FD1P3IX wr_data__i9 (.D(n500), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[9]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i9.GSR = "DISABLED";
    FD1P3IX wr_data__i8 (.D(n501), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[8]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i8.GSR = "DISABLED";
    FD1P3IX wr_data__i7 (.D(n502), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[7]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i7.GSR = "DISABLED";
    FD1P3IX wr_data__i6 (.D(n503), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[6]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i6.GSR = "DISABLED";
    FD1P3IX wr_data__i5 (.D(n504), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[5]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i5.GSR = "DISABLED";
    FD1P3IX wr_data__i4 (.D(n505), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[4]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i4.GSR = "DISABLED";
    FD1P3IX wr_data__i3 (.D(n506), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[3]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i3.GSR = "DISABLED";
    FD1P3IX wr_data__i2 (.D(n507), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[2]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i2.GSR = "DISABLED";
    LUT4 i2034_2_lut (.A(cmd_data[14]), .B(n15), .Z(n495)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2034_2_lut.init = 16'h8888;
    FD1P3IX wr_data__i1 (.D(n508), .SP(clk_c_enable_102), .CD(n3702), 
            .CK(clk_c), .Q(wr_data[1]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_data__i1.GSR = "DISABLED";
    LUT4 i2033_2_lut (.A(cmd_data[13]), .B(n15), .Z(n496)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2033_2_lut.init = 16'hbbbb;
    LUT4 i2032_2_lut (.A(cmd_data[12]), .B(n15), .Z(n497)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2032_2_lut.init = 16'hbbbb;
    LUT4 i2031_2_lut (.A(cmd_data[11]), .B(n15), .Z(n498)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2031_2_lut.init = 16'h8888;
    LUT4 i2030_2_lut (.A(cmd_data[10]), .B(n15), .Z(n499)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2030_2_lut.init = 16'h8888;
    LUT4 i2029_2_lut (.A(cmd_data[9]), .B(n15), .Z(n500)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2029_2_lut.init = 16'h8888;
    LUT4 i2028_2_lut (.A(cmd_data[8]), .B(n15), .Z(n501)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2028_2_lut.init = 16'h8888;
    LUT4 i2027_2_lut (.A(cmd_data[7]), .B(n15), .Z(n502)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2027_2_lut.init = 16'h8888;
    LUT4 i2026_2_lut (.A(cmd_data[6]), .B(n15), .Z(n503)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2026_2_lut.init = 16'h8888;
    LUT4 i2025_2_lut (.A(cmd_data[5]), .B(n15), .Z(n504)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2025_2_lut.init = 16'hbbbb;
    LUT4 i2024_2_lut (.A(cmd_data[4]), .B(n15), .Z(n505)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2024_2_lut.init = 16'hbbbb;
    FD1P3IX led_status__i2 (.D(cmd_data[2]), .SP(clk_c_enable_157), .CD(n3702), 
            .CK(clk_c), .Q(led_status[2]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam led_status__i2.GSR = "DISABLED";
    LUT4 i2022_2_lut (.A(cmd_data[3]), .B(n15), .Z(n506)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2022_2_lut.init = 16'h8888;
    GSR GSR_INST (.GSR(rst_n));
    FD1P3IX led_status__i1 (.D(cmd_data[1]), .SP(clk_c_enable_157), .CD(n3702), 
            .CK(clk_c), .Q(led_status[1]));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam led_status__i1.GSR = "DISABLED";
    OB led_pad (.I(led_c), .O(led));   // f:/home/mini-step-fpga/prj/template/top.v(5[9:12])
    FD1S3IX wr_18 (.D(valid_o), .CK(clk_c), .CD(n3702), .Q(wr));   // f:/home/mini-step-fpga/prj/template/top.v(34[8] 51[4])
    defparam wr_18.GSR = "DISABLED";
    LUT4 i2021_2_lut (.A(cmd_data[2]), .B(n15), .Z(n507)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2021_2_lut.init = 16'h8888;
    LUT4 i2020_2_lut (.A(cmd_data[1]), .B(n15), .Z(n508)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2020_2_lut.init = 16'h8888;
    LUT4 i2051_2_lut (.A(cmd_data[31]), .B(n15), .Z(n478)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2051_2_lut.init = 16'h8888;
    LUT4 i2050_2_lut (.A(cmd_data[30]), .B(n15), .Z(n479)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2050_2_lut.init = 16'h8888;
    LUT4 i2049_2_lut (.A(cmd_data[29]), .B(n15), .Z(n480)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2049_2_lut.init = 16'hbbbb;
    LedStatus LedStatus (.led_c(led_c), .clk_c(clk_c), .led_status({led_status}), 
            .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(27[3] 32[2])
    TSALL TSALL_INST (.TSALL(GND_net));
    LUT4 i2048_2_lut (.A(cmd_data[28]), .B(n15), .Z(n481)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2048_2_lut.init = 16'hbbbb;
    LUT4 i2047_2_lut (.A(cmd_data[27]), .B(n15), .Z(n482)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2047_2_lut.init = 16'h8888;
    LUT4 i2046_2_lut (.A(cmd_data[26]), .B(n15), .Z(n483)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2046_2_lut.init = 16'h8888;
    LUT4 i329_4_lut (.A(n3461), .B(rst_n), .C(cmd[0]), .D(valid_o), 
         .Z(clk_c_enable_157)) /* synthesis lut_function=(!(A (B)+!A !((C (D))+!B))) */ ;
    defparam i329_4_lut.init = 16'h7333;
    LUT4 i2045_2_lut (.A(cmd_data[25]), .B(n15), .Z(n484)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2045_2_lut.init = 16'h8888;
    LUT4 i2044_2_lut (.A(cmd_data[24]), .B(n15), .Z(n485)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2044_2_lut.init = 16'h8888;
    LUT4 i2043_2_lut (.A(cmd_data[23]), .B(n15), .Z(n486)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2043_2_lut.init = 16'h8888;
    LUT4 i2041_2_lut (.A(cmd_data[21]), .B(n15), .Z(n488)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2041_2_lut.init = 16'hbbbb;
    LUT4 i2042_2_lut (.A(cmd_data[22]), .B(n15), .Z(n487)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2042_2_lut.init = 16'h8888;
    VLO i1 (.Z(GND_net));
    LUT4 i2039_2_lut (.A(cmd_data[19]), .B(n15), .Z(n490)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2039_2_lut.init = 16'h8888;
    LUT4 m1_lut (.Z(n3971)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
    defparam m1_lut.init = 16'hffff;
    LUT4 i2038_2_lut (.A(cmd_data[18]), .B(n15), .Z(n491)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2038_2_lut.init = 16'h8888;
    LUT4 i2037_2_lut (.A(cmd_data[17]), .B(n15), .Z(n492)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2037_2_lut.init = 16'h8888;
    LUT4 i2922_4_lut (.A(cmd[4]), .B(cmd[6]), .C(cmd[5]), .D(cmd[2]), 
         .Z(n3455)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2922_4_lut.init = 16'hfffe;
    LUT4 i2040_2_lut (.A(cmd_data[20]), .B(n15), .Z(n489)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i2040_2_lut.init = 16'hbbbb;
    LUT4 i1963_2_lut (.A(cmd_data[0]), .B(n15), .Z(n509)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(42[4] 47[11])
    defparam i1963_2_lut.init = 16'h8888;
    LUT4 i7_4_lut (.A(n13), .B(cmd[7]), .C(n3701), .D(cmd[5]), .Z(n15)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(44[5:9])
    defparam i7_4_lut.init = 16'hfffe;
    LUT4 i5_4_lut (.A(cmd[0]), .B(cmd[2]), .C(cmd[6]), .D(cmd[4]), .Z(n13)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/top.v(44[5:9])
    defparam i5_4_lut.init = 16'hfffe;
    Rst_sys Rst_sys_uu (.rst_n(rst_n), .clk_c(clk_c), .GND_net(GND_net)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(14[10:32])
    PUR PUR_INST (.PUR(VCC_net));
    defparam PUR_INST.RST_PULSE = 1;
    Debug_core Debug_uut (.wr_data({wr_data}), .clk_c(clk_c), .rst_n(rst_n), 
            .wr(wr), .tx_c(tx_c), .GND_net(GND_net), .rx_c(rx_c), .cmd_data({cmd_data}), 
            .cmd({cmd}), .n3702(n3702), .valid_o(valid_o), .clk_c_enable_102(clk_c_enable_102), 
            .n3971(n3971)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(57[3] 68[2])
    VHI i3098 (.Z(VCC_net));
    
endmodule
//
// Verilog Description of module LedStatus
//

module LedStatus (led_c, clk_c, led_status, GND_net) /* synthesis syn_module_defined=1 */ ;
    output led_c;
    input clk_c;
    input [2:0]led_status;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    
    wire clk_c_enable_2, led_N_292, n45, n3433, n1810, n3614, n3613, 
        n3615;
    wire [31:0]cnt;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    
    wire clk_c_enable_139;
    wire [31:0]n133;
    
    wire n3464, n22, n28, n50, n3693, n3443, n3710, n3704, n1677, 
        n3331, n3083, n3081, n66, n3086, n3387, n3036, n3609, 
        n3170, n3611, n3075, n3378, n2587, n3167, n3390, n4, 
        n3363, n3385, n2812, n42, n3328, n55, n2756, n4_adj_692, 
        n3367, n3381, n3401, n2754, n3399, n3353, n3366, n2796, 
        n9, n4_adj_693, n3017, n3018, n3016, n3015, n3169, n3014, 
        n1695, n46, n3470, n2816, n3332, n3612, n3688, n3421, 
        n61, n3048, n3383, n62, n24, n3708, n18, n2340, n1537, 
        n40, n44, n18_adj_694, n3694, n36, n3471, n3397, n3511, 
        n6, n12, n4_adj_695, n70, n8, n4_adj_696, n3388, n3097, 
        n3029, n3028, n3027, n3026, n3025, n3024, n3023, n3022, 
        n3021, n3020, n3019;
    
    FD1P3AY led_36 (.D(led_N_292), .SP(clk_c_enable_2), .CK(clk_c), .Q(led_c)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=27, LSE_RLINE=32 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(52[10] 78[8])
    defparam led_36.GSR = "ENABLED";
    LUT4 i2955_4_lut (.A(led_status[2]), .B(n45), .C(led_status[1]), .D(n3433), 
         .Z(n1810)) /* synthesis lut_function=(!(A (B)+!A (B+!(C (D))))) */ ;
    defparam i2955_4_lut.init = 16'h3222;
    PFUMX i2987 (.BLUT(n3614), .ALUT(n3613), .C0(led_status[1]), .Z(n3615));
    FD1P3IX cnt_319__i13 (.D(n133[13]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[13])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i13.GSR = "ENABLED";
    FD1P3IX cnt_319__i12 (.D(n133[12]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[12])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i12.GSR = "ENABLED";
    LUT4 i49_4_lut (.A(n3464), .B(n22), .C(led_status[1]), .D(n28), 
         .Z(n45)) /* synthesis lut_function=(A (B+((D)+!C))+!A (B (C)+!B (C (D)))) */ ;
    defparam i49_4_lut.init = 16'hfaca;
    LUT4 i2900_4_lut (.A(led_status[0]), .B(n50), .C(n3693), .D(cnt[25]), 
         .Z(n3433)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2900_4_lut.init = 16'hfefa;
    LUT4 i2_4_lut (.A(cnt[25]), .B(led_status[0]), .C(n3693), .D(n3443), 
         .Z(n22)) /* synthesis lut_function=(!(A+((C+(D))+!B))) */ ;
    defparam i2_4_lut.init = 16'h0004;
    LUT4 i1_2_lut_rep_61 (.A(cnt[9]), .B(cnt[8]), .Z(n3710)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_61.init = 16'h8888;
    LUT4 i1_2_lut_rep_55 (.A(cnt[14]), .B(cnt[13]), .Z(n3704)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_55.init = 16'heeee;
    LUT4 i2_3_lut_4_lut (.A(n3693), .B(n1677), .C(cnt[22]), .D(cnt[21]), 
         .Z(n3331)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2_3_lut_4_lut.init = 16'hfffe;
    LUT4 i2_4_lut_adj_20 (.A(cnt[18]), .B(n3083), .C(cnt[17]), .D(cnt[16]), 
         .Z(n3081)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut_adj_20.init = 16'hfefa;
    LUT4 i1_2_lut_3_lut (.A(cnt[9]), .B(cnt[8]), .C(cnt[10]), .Z(n66)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut.init = 16'hf8f8;
    FD1P3IX cnt_319__i29 (.D(n133[29]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[29])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i29.GSR = "ENABLED";
    LUT4 i2_4_lut_adj_21 (.A(cnt[15]), .B(n3086), .C(cnt[14]), .D(cnt[13]), 
         .Z(n3083)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i2_4_lut_adj_21.init = 16'hfefa;
    FD1P3IX cnt_319__i31 (.D(n133[31]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[31])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i31.GSR = "ENABLED";
    FD1P3IX cnt_319__i28 (.D(n133[28]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[28])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i28.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_adj_22 (.A(cnt[16]), .B(cnt[15]), .C(cnt[17]), 
         .Z(n3387)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_22.init = 16'h8080;
    FD1P3IX cnt_319__i22 (.D(n133[22]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[22])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i22.GSR = "ENABLED";
    FD1P3IX cnt_319__i30 (.D(n133[30]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[30])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i30.GSR = "ENABLED";
    FD1P3IX cnt_319__i23 (.D(n133[23]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[23])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i23.GSR = "ENABLED";
    FD1P3IX cnt_319__i24 (.D(n133[24]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[24])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i24.GSR = "ENABLED";
    FD1P3IX cnt_319__i25 (.D(n133[25]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[25])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i25.GSR = "ENABLED";
    FD1P3IX cnt_319__i26 (.D(n133[26]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[26])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i26.GSR = "ENABLED";
    FD1P3IX cnt_319__i27 (.D(n133[27]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[27])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i27.GSR = "ENABLED";
    FD1P3IX cnt_319__i21 (.D(n133[21]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[21])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i21.GSR = "ENABLED";
    LUT4 i2_3_lut (.A(cnt[12]), .B(n3036), .C(cnt[11]), .Z(n3086)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i2_3_lut.init = 16'hfefe;
    FD1P3IX cnt_319__i20 (.D(n133[20]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[20])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i20.GSR = "ENABLED";
    LUT4 i3_4_lut (.A(cnt[6]), .B(n3710), .C(cnt[10]), .D(cnt[7]), .Z(n3036)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i3_4_lut.init = 16'h8000;
    FD1P3IX cnt_319__i19 (.D(n133[19]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[19])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i19.GSR = "ENABLED";
    LUT4 n3610_bdd_2_lut_3_lut (.A(n3609), .B(cnt[24]), .C(n3170), .Z(n3611)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam n3610_bdd_2_lut_3_lut.init = 16'hfefe;
    FD1P3IX cnt_319__i18 (.D(n133[18]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[18])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i18.GSR = "ENABLED";
    FD1P3IX cnt_319__i17 (.D(n133[17]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[17])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i17.GSR = "ENABLED";
    FD1P3IX cnt_319__i16 (.D(n133[16]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[16])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i16.GSR = "ENABLED";
    LUT4 i2_3_lut_4_lut_adj_23 (.A(cnt[16]), .B(cnt[15]), .C(n3075), .D(cnt[14]), 
         .Z(n3378)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i2_3_lut_4_lut_adj_23.init = 16'h8000;
    LUT4 i2093_2_lut (.A(cnt[19]), .B(cnt[20]), .Z(n2587)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2093_2_lut.init = 16'h8888;
    FD1P3IX cnt_319__i15 (.D(n133[15]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[15])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i15.GSR = "ENABLED";
    FD1P3IX cnt_319__i14 (.D(n133[14]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[14])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i14.GSR = "ENABLED";
    LUT4 i1_4_lut (.A(cnt[18]), .B(n3167), .C(n3387), .D(n3390), .Z(n4)) /* synthesis lut_function=(A+(B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_4_lut.init = 16'hfaea;
    LUT4 i1_4_lut_adj_24 (.A(n3363), .B(cnt[7]), .C(cnt[9]), .D(cnt[8]), 
         .Z(n3167)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_24.init = 16'ha8a0;
    LUT4 i1_4_lut_adj_25 (.A(cnt[17]), .B(cnt[19]), .C(n3378), .D(cnt[18]), 
         .Z(n3385)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;
    defparam i1_4_lut_adj_25.init = 16'hc800;
    FD1P3IX cnt_319__i11 (.D(n133[11]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[11])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i11.GSR = "ENABLED";
    FD1P3IX cnt_319__i10 (.D(n133[10]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i10.GSR = "ENABLED";
    FD1P3IX cnt_319__i9 (.D(n133[9]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i9.GSR = "ENABLED";
    LUT4 i1_2_lut_3_lut_adj_26 (.A(cnt[14]), .B(cnt[13]), .C(cnt[12]), 
         .Z(n3390)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_3_lut_adj_26.init = 16'hfefe;
    FD1P3IX cnt_319__i8 (.D(n133[8]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i8.GSR = "ENABLED";
    FD1P3IX cnt_319__i7 (.D(n133[7]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i7.GSR = "ENABLED";
    LUT4 i2_4_lut_adj_27 (.A(cnt[12]), .B(n2812), .C(cnt[13]), .D(cnt[11]), 
         .Z(n3075)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i2_4_lut_adj_27.init = 16'hfffe;
    LUT4 i1_4_lut_adj_28 (.A(led_status[2]), .B(led_status[0]), .C(n42), 
         .D(n3331), .Z(n28)) /* synthesis lut_function=(A (B+!(C+(D)))) */ ;
    defparam i1_4_lut_adj_28.init = 16'h888a;
    LUT4 cnt_24__bdd_4_lut (.A(n3328), .B(cnt[31]), .C(cnt[25]), .D(cnt[23]), 
         .Z(n3609)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam cnt_24__bdd_4_lut.init = 16'hfffe;
    FD1P3IX cnt_319__i6 (.D(n133[6]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i6.GSR = "ENABLED";
    FD1P3IX cnt_319__i5 (.D(n133[5]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i5.GSR = "ENABLED";
    FD1P3IX cnt_319__i4 (.D(n133[4]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i4.GSR = "ENABLED";
    FD1P3IX cnt_319__i3 (.D(n133[3]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i3.GSR = "ENABLED";
    FD1P3IX cnt_319__i2 (.D(n133[2]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i2.GSR = "ENABLED";
    FD1P3IX cnt_319__i1 (.D(n133[1]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i1.GSR = "ENABLED";
    LUT4 i2312_4_lut (.A(n55), .B(cnt[6]), .C(cnt[8]), .D(cnt[7]), .Z(n2812)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;
    defparam i2312_4_lut.init = 16'ha8a0;
    FD1P3IX cnt_319__i0 (.D(n133[0]), .SP(clk_c_enable_139), .CD(n1810), 
            .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319__i0.GSR = "ENABLED";
    LUT4 i1_4_lut_adj_29 (.A(cnt[22]), .B(cnt[24]), .C(cnt[23]), .D(n2756), 
         .Z(n4_adj_692)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i1_4_lut_adj_29.init = 16'hfcec;
    LUT4 i2910_3_lut (.A(n3367), .B(cnt[24]), .C(cnt[23]), .Z(n3443)) /* synthesis lut_function=(A (B)+!A (B (C))) */ ;
    defparam i2910_3_lut.init = 16'hc8c8;
    LUT4 i1_2_lut (.A(cnt[10]), .B(cnt[9]), .Z(n55)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_2_lut.init = 16'h8888;
    LUT4 i2259_4_lut (.A(cnt[20]), .B(n3381), .C(cnt[19]), .D(n3401), 
         .Z(n2754)) /* synthesis lut_function=(A+(B (C (D)))) */ ;
    defparam i2259_4_lut.init = 16'heaaa;
    LUT4 i1_4_lut_adj_30 (.A(n55), .B(n3399), .C(n3353), .D(cnt[11]), 
         .Z(n3401)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_30.init = 16'hfcec;
    LUT4 i2297_4_lut (.A(n2754), .B(cnt[24]), .C(cnt[23]), .D(n3366), 
         .Z(n2796)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i2297_4_lut.init = 16'hc8c0;
    LUT4 i1_2_lut_adj_31 (.A(cnt[22]), .B(cnt[21]), .Z(n3366)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_31.init = 16'h8888;
    LUT4 i1_4_lut_adj_32 (.A(cnt[20]), .B(cnt[19]), .C(cnt[21]), .D(n9), 
         .Z(n2756)) /* synthesis lut_function=(A (B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_32.init = 16'ha080;
    LUT4 i2_4_lut_adj_33 (.A(n3704), .B(cnt[16]), .C(n4_adj_693), .D(n3381), 
         .Z(n9)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i2_4_lut_adj_33.init = 16'hc800;
    LUT4 i1_4_lut_adj_34 (.A(cnt[11]), .B(cnt[15]), .C(n66), .D(cnt[12]), 
         .Z(n4_adj_693)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_4_lut_adj_34.init = 16'heccc;
    CCU2D cnt_319_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3017), 
          .COUT(n3018), .S0(n133[7]), .S1(n133[8]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_9.INJECT1_0 = "NO";
    defparam cnt_319_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3016), 
          .COUT(n3017), .S0(n133[5]), .S1(n133[6]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_7.INJECT1_0 = "NO";
    defparam cnt_319_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3015), 
          .COUT(n3016), .S0(n133[3]), .S1(n133[4]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_5.INJECT1_0 = "NO";
    defparam cnt_319_add_4_5.INJECT1_1 = "NO";
    LUT4 i1_4_lut_adj_35 (.A(cnt[20]), .B(cnt[22]), .C(cnt[21]), .D(n3385), 
         .Z(n3169)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(66[24:49])
    defparam i1_4_lut_adj_35.init = 16'hfcec;
    CCU2D cnt_319_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3014), 
          .COUT(n3015), .S0(n133[1]), .S1(n133[2]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_3.INJECT1_0 = "NO";
    defparam cnt_319_add_4_3.INJECT1_1 = "NO";
    LUT4 i2942_1_lut_4_lut (.A(n1695), .B(n46), .C(cnt[24]), .D(cnt[23]), 
         .Z(n3470)) /* synthesis lut_function=(!(A+(B (C+(D))+!B (C)))) */ ;
    defparam i2942_1_lut_4_lut.init = 16'h0105;
    LUT4 i2316_4_lut (.A(cnt[21]), .B(cnt[22]), .C(n2587), .D(n4), .Z(n2816)) /* synthesis lut_function=(A (B)+!A (B (C (D)))) */ ;
    defparam i2316_4_lut.init = 16'hc888;
    PFUMX i2985 (.BLUT(n3611), .ALUT(n3332), .C0(led_status[1]), .Z(n3612));
    CCU2D cnt_319_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3014), 
          .S1(n133[0]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_1.INIT0 = 16'hF000;
    defparam cnt_319_add_4_1.INIT1 = 16'h0555;
    defparam cnt_319_add_4_1.INJECT1_0 = "NO";
    defparam cnt_319_add_4_1.INJECT1_1 = "NO";
    LUT4 i2_4_lut_adj_36 (.A(n3331), .B(n3081), .C(cnt[20]), .D(cnt[19]), 
         .Z(n3332)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(74[24:52])
    defparam i2_4_lut_adj_36.init = 16'hfefa;
    LUT4 i1_2_lut_rep_44 (.A(n3328), .B(cnt[31]), .Z(n3693)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_2_lut_rep_44.init = 16'heeee;
    LUT4 i1_2_lut_rep_39_3_lut (.A(n3328), .B(cnt[31]), .C(n1677), .Z(n3688)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_rep_39_3_lut.init = 16'hfefe;
    LUT4 n3421_bdd_4_lut_3004 (.A(n3421), .B(n3328), .C(cnt[31]), .D(cnt[25]), 
         .Z(n3613)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam n3421_bdd_4_lut_3004.init = 16'hfffe;
    LUT4 i2967_3_lut (.A(led_status[1]), .B(led_status[2]), .C(led_status[0]), 
         .Z(clk_c_enable_2)) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i2967_3_lut.init = 16'h7f7f;
    LUT4 i2_4_lut_adj_37 (.A(n61), .B(cnt[14]), .C(cnt[12]), .D(cnt[13]), 
         .Z(n3048)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i2_4_lut_adj_37.init = 16'hc800;
    LUT4 i1_4_lut_adj_38 (.A(n3383), .B(cnt[22]), .C(cnt[20]), .D(cnt[21]), 
         .Z(n3367)) /* synthesis lut_function=(A (B (D))+!A (B (C (D)))) */ ;
    defparam i1_4_lut_adj_38.init = 16'hc800;
    LUT4 i2_4_lut_adj_39 (.A(cnt[17]), .B(cnt[19]), .C(cnt[18]), .D(n62), 
         .Z(n3383)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2_4_lut_adj_39.init = 16'h8000;
    LUT4 i1_4_lut_adj_40 (.A(n24), .B(cnt[14]), .C(n3353), .D(n3708), 
         .Z(n62)) /* synthesis lut_function=(A (B+(C+(D)))+!A (B+(D))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_40.init = 16'hffec;
    LUT4 i74_4_lut (.A(cnt[11]), .B(n18), .C(cnt[10]), .D(cnt[9]), .Z(n61)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i74_4_lut.init = 16'ha8a0;
    LUT4 i1_2_lut_3_lut_adj_41 (.A(n3328), .B(cnt[31]), .C(cnt[25]), .Z(n1695)) /* synthesis lut_function=(A+(B+(C))) */ ;
    defparam i1_2_lut_3_lut_adj_41.init = 16'hfefe;
    LUT4 i553_4_lut (.A(n18), .B(cnt[11]), .C(cnt[10]), .D(cnt[9]), 
         .Z(n24)) /* synthesis lut_function=(A (B+(C))+!A (B+(C (D)))) */ ;
    defparam i553_4_lut.init = 16'hfcec;
    LUT4 i1_2_lut_3_lut_adj_42 (.A(cnt[7]), .B(n2340), .C(cnt[8]), .Z(n18)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_42.init = 16'h8080;
    LUT4 i582_4_lut (.A(n3381), .B(cnt[19]), .C(cnt[16]), .D(n1537), 
         .Z(n40)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i582_4_lut.init = 16'heccc;
    LUT4 i533_4_lut (.A(cnt[23]), .B(cnt[24]), .C(cnt[22]), .D(n44), 
         .Z(n50)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i533_4_lut.init = 16'heccc;
    LUT4 i1_2_lut_3_lut_adj_43 (.A(cnt[7]), .B(n2340), .C(cnt[8]), .Z(n18_adj_694)) /* synthesis lut_function=(A (B+(C))+!A (C)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_43.init = 16'hf8f8;
    LUT4 n3421_bdd_1_lut_3005 (.A(led_status[0]), .Z(n3614)) /* synthesis lut_function=(!(A)) */ ;
    defparam n3421_bdd_1_lut_3005.init = 16'h5555;
    LUT4 i1_2_lut_rep_45 (.A(cnt[7]), .B(n2340), .Z(n3694)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_45.init = 16'heeee;
    LUT4 i479_4_lut (.A(cnt[19]), .B(cnt[20]), .C(cnt[18]), .D(n36), 
         .Z(n42)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i479_4_lut.init = 16'hccc8;
    PFUMX i51 (.BLUT(n3470), .ALUT(n3471), .C0(led_status[0]), .Z(n3464));
    LUT4 i476_4_lut (.A(cnt[14]), .B(cnt[17]), .C(n3708), .D(n3397), 
         .Z(n36)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i476_4_lut.init = 16'hc8c0;
    LUT4 i1_4_lut_adj_44 (.A(cnt[9]), .B(n3511), .C(n6), .D(n3694), 
         .Z(n3397)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i1_4_lut_adj_44.init = 16'heccc;
    LUT4 i1_rep_14_2_lut (.A(cnt[12]), .B(cnt[13]), .Z(n3511)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i1_rep_14_2_lut.init = 16'heeee;
    LUT4 i2_3_lut_adj_45 (.A(cnt[8]), .B(cnt[11]), .C(cnt[10]), .Z(n6)) /* synthesis lut_function=(A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i2_3_lut_adj_45.init = 16'h8080;
    LUT4 i6_4_lut (.A(cnt[1]), .B(n12), .C(cnt[0]), .D(cnt[5]), .Z(n2340)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i6_4_lut.init = 16'h8000;
    LUT4 i5_4_lut (.A(cnt[3]), .B(cnt[4]), .C(cnt[6]), .D(cnt[2]), .Z(n12)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i5_4_lut.init = 16'h8000;
    LUT4 i514_4_lut (.A(cnt[19]), .B(cnt[21]), .C(n4_adj_695), .D(cnt[18]), 
         .Z(n44)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i514_4_lut.init = 16'heccc;
    LUT4 i82_3_lut_4_lut (.A(cnt[7]), .B(n2340), .C(cnt[8]), .D(cnt[9]), 
         .Z(n70)) /* synthesis lut_function=(A (C+(D))+!A (B (C+(D))+!B (D))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i82_3_lut_4_lut.init = 16'hffe0;
    LUT4 i1_2_lut_adj_46 (.A(cnt[12]), .B(cnt[13]), .Z(n3353)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_46.init = 16'h8888;
    LUT4 i2_3_lut_adj_47 (.A(cnt[24]), .B(cnt[23]), .C(cnt[25]), .Z(n1677)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(66[24:49])
    defparam i2_3_lut_adj_47.init = 16'hfefe;
    LUT4 i3_4_lut_adj_48 (.A(cnt[26]), .B(cnt[29]), .C(n8), .D(cnt[27]), 
         .Z(n3328)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ;
    defparam i3_4_lut_adj_48.init = 16'hfffe;
    LUT4 i2_2_lut (.A(cnt[30]), .B(cnt[28]), .Z(n8)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2_2_lut.init = 16'heeee;
    LUT4 i1_4_lut_adj_49 (.A(cnt[15]), .B(cnt[12]), .C(n3704), .D(n4_adj_696), 
         .Z(n1537)) /* synthesis lut_function=(A+(B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_49.init = 16'hfefa;
    LUT4 i1_4_lut_adj_50 (.A(cnt[11]), .B(n18_adj_694), .C(cnt[10]), .D(cnt[9]), 
         .Z(n4_adj_696)) /* synthesis lut_function=(A (B (C+(D))+!B (C))) */ ;
    defparam i1_4_lut_adj_50.init = 16'ha8a0;
    LUT4 i1_2_lut_adj_51 (.A(cnt[17]), .B(cnt[18]), .Z(n3381)) /* synthesis lut_function=(A (B)) */ ;
    defparam i1_2_lut_adj_51.init = 16'h8888;
    LUT4 i585_4_lut (.A(cnt[21]), .B(cnt[22]), .C(cnt[20]), .D(n40), 
         .Z(n46)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i585_4_lut.init = 16'heccc;
    LUT4 i1_4_lut_adj_52 (.A(cnt[20]), .B(n3708), .C(n3048), .D(cnt[17]), 
         .Z(n4_adj_695)) /* synthesis lut_function=(A (B+(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_52.init = 16'haaa8;
    PFUMX i2638 (.BLUT(n2816), .ALUT(n3169), .C0(led_status[0]), .Z(n3170));
    LUT4 i2_4_lut_adj_53 (.A(cnt[19]), .B(n3388), .C(cnt[20]), .D(cnt[18]), 
         .Z(n3097)) /* synthesis lut_function=(A (B (C)+!B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i2_4_lut_adj_53.init = 16'ha080;
    LUT4 i2943_1_lut_4_lut (.A(n3097), .B(n3688), .C(cnt[22]), .D(cnt[21]), 
         .Z(n3471)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C (D))))) */ ;
    defparam i2943_1_lut_4_lut.init = 16'h0313;
    LUT4 i1_2_lut_rep_59 (.A(cnt[15]), .B(cnt[16]), .Z(n3708)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_rep_59.init = 16'heeee;
    PFUMX status_2__I_0_i2 (.BLUT(n2796), .ALUT(n4_adj_692), .C0(led_status[0]), 
          .Z(n3421)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=27, LSE_RLINE=32 */ ;
    LUT4 i1_4_lut_adj_54 (.A(n70), .B(n3387), .C(n3390), .D(n3363), 
         .Z(n3388)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_4_lut_adj_54.init = 16'hc8c0;
    LUT4 i1_2_lut_adj_55 (.A(cnt[11]), .B(cnt[10]), .Z(n3363)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(46[16:19])
    defparam i1_2_lut_adj_55.init = 16'h8888;
    L6MUX21 i2989 (.D0(n3615), .D1(n3612), .SD(led_status[2]), .Z(led_N_292));
    LUT4 i1_2_lut_3_lut_adj_56 (.A(cnt[15]), .B(cnt[16]), .C(cnt[14]), 
         .Z(n3399)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam i1_2_lut_3_lut_adj_56.init = 16'hfefe;
    CCU2D cnt_319_add_4_33 (.A0(cnt[31]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(GND_net), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3029), .S0(n133[31]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_33.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_33.INIT1 = 16'h0000;
    defparam cnt_319_add_4_33.INJECT1_0 = "NO";
    defparam cnt_319_add_4_33.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_31 (.A0(cnt[29]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[30]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3028), .COUT(n3029), .S0(n133[29]), .S1(n133[30]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_31.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_31.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_31.INJECT1_0 = "NO";
    defparam cnt_319_add_4_31.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_29 (.A0(cnt[27]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[28]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3027), .COUT(n3028), .S0(n133[27]), .S1(n133[28]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_29.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_29.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_29.INJECT1_0 = "NO";
    defparam cnt_319_add_4_29.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_27 (.A0(cnt[25]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[26]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3026), .COUT(n3027), .S0(n133[25]), .S1(n133[26]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_27.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_27.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_27.INJECT1_0 = "NO";
    defparam cnt_319_add_4_27.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_25 (.A0(cnt[23]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[24]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3025), .COUT(n3026), .S0(n133[23]), .S1(n133[24]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_25.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_25.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_25.INJECT1_0 = "NO";
    defparam cnt_319_add_4_25.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_23 (.A0(cnt[21]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[22]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3024), .COUT(n3025), .S0(n133[21]), .S1(n133[22]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_23.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_23.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_23.INJECT1_0 = "NO";
    defparam cnt_319_add_4_23.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_21 (.A0(cnt[19]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[20]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3023), .COUT(n3024), .S0(n133[19]), .S1(n133[20]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_21.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_21.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_21.INJECT1_0 = "NO";
    defparam cnt_319_add_4_21.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_19 (.A0(cnt[17]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[18]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3022), .COUT(n3023), .S0(n133[17]), .S1(n133[18]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_19.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_19.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_19.INJECT1_0 = "NO";
    defparam cnt_319_add_4_19.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_17 (.A0(cnt[15]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[16]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3021), .COUT(n3022), .S0(n133[15]), .S1(n133[16]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_17.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_17.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_17.INJECT1_0 = "NO";
    defparam cnt_319_add_4_17.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_15 (.A0(cnt[13]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[14]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3020), .COUT(n3021), .S0(n133[13]), .S1(n133[14]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_15.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_15.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_15.INJECT1_0 = "NO";
    defparam cnt_319_add_4_15.INJECT1_1 = "NO";
    CCU2D cnt_319_add_4_13 (.A0(cnt[11]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(cnt[12]), .B1(GND_net), .C1(GND_net), .D1(GND_net), 
          .CIN(n3019), .COUT(n3020), .S0(n133[11]), .S1(n133[12]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_13.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_13.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_13.INJECT1_0 = "NO";
    defparam cnt_319_add_4_13.INJECT1_1 = "NO";
    LUT4 i12_3_lut (.A(led_status[1]), .B(led_status[0]), .C(led_status[2]), 
         .Z(clk_c_enable_139)) /* synthesis lut_function=(!(A (B (C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(53[9] 77[16])
    defparam i12_3_lut.init = 16'h7a7a;
    CCU2D cnt_319_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3018), 
          .COUT(n3019), .S0(n133[9]), .S1(n133[10]));   // f:/home/mini-step-fpga/prj/template/ledstatus.v(73[56:66])
    defparam cnt_319_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_319_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_319_add_4_11.INJECT1_0 = "NO";
    defparam cnt_319_add_4_11.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box. 
//

//
// Verilog Description of module Rst_sys
//

module Rst_sys (rst_n, clk_c, GND_net) /* synthesis syn_module_defined=1 */ ;
    output rst_n;
    input clk_c;
    input GND_net;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    
    wire n3689;
    wire [10:0]cnt;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(30[25:28])
    
    wire n6, cnt_10__N_96;
    wire [10:0]n49;
    
    wire n2746, n3011, n3012, n3010, n3009, n2780, n3008;
    
    FD1S3AX rst_n_11 (.D(n3689), .CK(clk_c), .Q(rst_n)) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=10, LSE_RCOL=32, LSE_LLINE=14, LSE_RLINE=14 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(40[7] 43[21])
    defparam rst_n_11.GSR = "DISABLED";
    LUT4 i2_2_lut (.A(cnt[1]), .B(cnt[2]), .Z(n6)) /* synthesis lut_function=(A (B)) */ ;
    defparam i2_2_lut.init = 16'h8888;
    FD1P3AX cnt_318__i0 (.D(n49[0]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i0.GSR = "DISABLED";
    LUT4 i2252_4_lut (.A(cnt[0]), .B(cnt[4]), .C(n6), .D(cnt[3]), .Z(n2746)) /* synthesis lut_function=(A (B+(C (D)))+!A (B)) */ ;
    defparam i2252_4_lut.init = 16'heccc;
    CCU2D cnt_318_add_4_9 (.A0(cnt[7]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[8]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3011), 
          .COUT(n3012), .S0(n49[7]), .S1(n49[8]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_9.INIT0 = 16'hfaaa;
    defparam cnt_318_add_4_9.INIT1 = 16'hfaaa;
    defparam cnt_318_add_4_9.INJECT1_0 = "NO";
    defparam cnt_318_add_4_9.INJECT1_1 = "NO";
    CCU2D cnt_318_add_4_7 (.A0(cnt[5]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[6]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3010), 
          .COUT(n3011), .S0(n49[5]), .S1(n49[6]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_7.INIT0 = 16'hfaaa;
    defparam cnt_318_add_4_7.INIT1 = 16'hfaaa;
    defparam cnt_318_add_4_7.INJECT1_0 = "NO";
    defparam cnt_318_add_4_7.INJECT1_1 = "NO";
    CCU2D cnt_318_add_4_5 (.A0(cnt[3]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[4]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3009), 
          .COUT(n3010), .S0(n49[3]), .S1(n49[4]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_5.INIT0 = 16'hfaaa;
    defparam cnt_318_add_4_5.INIT1 = 16'hfaaa;
    defparam cnt_318_add_4_5.INJECT1_0 = "NO";
    defparam cnt_318_add_4_5.INJECT1_1 = "NO";
    LUT4 i2301_4_lut_rep_40 (.A(cnt[9]), .B(cnt[10]), .C(n2780), .D(cnt[8]), 
         .Z(n3689)) /* synthesis lut_function=(A (B)+!A (B (C+(D)))) */ ;
    defparam i2301_4_lut_rep_40.init = 16'hccc8;
    LUT4 i2302_1_lut_4_lut (.A(cnt[9]), .B(cnt[10]), .C(n2780), .D(cnt[8]), 
         .Z(cnt_10__N_96)) /* synthesis lut_function=(!(A (B)+!A (B (C+(D))))) */ ;
    defparam i2302_1_lut_4_lut.init = 16'h3337;
    FD1P3AX cnt_318__i1 (.D(n49[1]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i1.GSR = "DISABLED";
    LUT4 i2283_4_lut (.A(n2746), .B(cnt[7]), .C(cnt[6]), .D(cnt[5]), 
         .Z(n2780)) /* synthesis lut_function=(A (B (C+(D)))+!A (B (C))) */ ;
    defparam i2283_4_lut.init = 16'hc8c0;
    FD1P3AX cnt_318__i2 (.D(n49[2]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i2.GSR = "DISABLED";
    FD1P3AX cnt_318__i3 (.D(n49[3]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i3.GSR = "DISABLED";
    FD1P3AX cnt_318__i4 (.D(n49[4]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i4.GSR = "DISABLED";
    FD1P3AX cnt_318__i5 (.D(n49[5]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i5.GSR = "DISABLED";
    FD1P3AX cnt_318__i6 (.D(n49[6]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i6.GSR = "DISABLED";
    FD1P3AX cnt_318__i7 (.D(n49[7]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[7])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i7.GSR = "DISABLED";
    FD1P3AX cnt_318__i8 (.D(n49[8]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[8])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i8.GSR = "DISABLED";
    FD1P3AX cnt_318__i9 (.D(n49[9]), .SP(cnt_10__N_96), .CK(clk_c), .Q(cnt[9])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i9.GSR = "DISABLED";
    FD1P3AX cnt_318__i10 (.D(n49[10]), .SP(cnt_10__N_96), .CK(clk_c), 
            .Q(cnt[10])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318__i10.GSR = "DISABLED";
    CCU2D cnt_318_add_4_3 (.A0(cnt[1]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[2]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3008), 
          .COUT(n3009), .S0(n49[1]), .S1(n49[2]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_3.INIT0 = 16'hfaaa;
    defparam cnt_318_add_4_3.INIT1 = 16'hfaaa;
    defparam cnt_318_add_4_3.INJECT1_0 = "NO";
    defparam cnt_318_add_4_3.INJECT1_1 = "NO";
    CCU2D cnt_318_add_4_11 (.A0(cnt[9]), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[10]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n3012), 
          .S0(n49[9]), .S1(n49[10]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_11.INIT0 = 16'hfaaa;
    defparam cnt_318_add_4_11.INIT1 = 16'hfaaa;
    defparam cnt_318_add_4_11.INJECT1_0 = "NO";
    defparam cnt_318_add_4_11.INJECT1_1 = "NO";
    CCU2D cnt_318_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), .D0(GND_net), 
          .A1(cnt[0]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .COUT(n3008), 
          .S1(n49[0]));   // f:/home/mini-step-fpga/prj/template/rst_sys.v(35[12:19])
    defparam cnt_318_add_4_1.INIT0 = 16'hF000;
    defparam cnt_318_add_4_1.INIT1 = 16'h0555;
    defparam cnt_318_add_4_1.INJECT1_0 = "NO";
    defparam cnt_318_add_4_1.INJECT1_1 = "NO";
    
endmodule
//
// Verilog Description of module PUR
// module not written out since it is a black-box. 
//

//
// Verilog Description of module Debug_core
//

module Debug_core (wr_data, clk_c, rst_n, wr, tx_c, GND_net, rx_c, 
            cmd_data, cmd, n3702, valid_o, clk_c_enable_102, n3971) /* synthesis syn_module_defined=1 */ ;
    input [31:0]wr_data;
    input clk_c;
    input rst_n;
    input wr;
    output tx_c;
    input GND_net;
    input rx_c;
    output [31:0]cmd_data;
    output [7:0]cmd;
    output n3702;
    output valid_o;
    output clk_c_enable_102;
    input n3971;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    wire [31:0]tx_buf;   // f:/home/mini-step-fpga/prj/template/debug_core.v(455[12:18])
    
    wire n308, n322, n323;
    wire [7:0]tdata;   // f:/home/mini-step-fpga/prj/template/debug_core.v(447[10:15])
    
    wire clk_c_enable_116;
    wire [2:0]cnt;   // f:/home/mini-step-fpga/prj/template/debug_core.v(443[11:14])
    
    wire clk_c_enable_146;
    wire [2:0]cnt_2__N_303;
    
    wire n324, n325, n326, n3699;
    wire [12:0]r_shift_12__N_666;
    
    wire n3712, n3711, n3703, n3691, n327, n328, n329, n330, 
        n331, clk_c_enable_193, n1809, n332, n333, n334, start, 
        n335, n317, n318, n319, n320, n321, n336, n337, n338, 
        n339, n340, tx_buf_31__N_412, n3348;
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/template/debug_core.v(232[17:28])
    wire [1:0]nstate;   // f:/home/mini-step-fpga/prj/template/debug_core.v(227[27:33])
    wire [7:0]rx_data;   // f:/home/mini-step-fpga/prj/template/debug_core.v(438[18:25])
    
    wire n3707;
    wire [2:0]cnt_adj_691;   // f:/home/mini-step-fpga/prj/template/debug_core.v(372[11:14])
    wire [2:0]cnt_2__N_615;
    
    LUT4 mux_88_i14_3_lut (.A(wr_data[13]), .B(tx_buf[5]), .C(n308), .Z(n322)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i14_3_lut.init = 16'hcaca;
    LUT4 mux_88_i15_3_lut (.A(wr_data[14]), .B(tx_buf[6]), .C(n308), .Z(n323)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i15_3_lut.init = 16'hcaca;
    FD1P3AX tdata_i0_i0 (.D(tx_buf[24]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i0.GSR = "DISABLED";
    FD1P3AX cnt_i0 (.D(cnt_2__N_303[0]), .SP(clk_c_enable_146), .CK(clk_c), 
            .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam cnt_i0.GSR = "ENABLED";
    LUT4 mux_88_i16_3_lut (.A(wr_data[15]), .B(tx_buf[7]), .C(n308), .Z(n324)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i16_3_lut.init = 16'hcaca;
    LUT4 mux_88_i17_3_lut (.A(wr_data[16]), .B(tx_buf[8]), .C(n308), .Z(n325)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i17_3_lut.init = 16'hcaca;
    LUT4 mux_88_i18_3_lut (.A(wr_data[17]), .B(tx_buf[9]), .C(n308), .Z(n326)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i18_3_lut.init = 16'hcaca;
    LUT4 i1_3_lut_then_3_lut (.A(n3699), .B(r_shift_12__N_666[12]), .C(cnt[0]), 
         .Z(n3712)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
    defparam i1_3_lut_then_3_lut.init = 16'h4040;
    LUT4 i1_3_lut_else_3_lut (.A(n3699), .B(r_shift_12__N_666[12]), .C(cnt[0]), 
         .D(cnt[2]), .Z(n3711)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam i1_3_lut_else_3_lut.init = 16'h0400;
    FD1P3AX tdata_i0_i7 (.D(tx_buf[31]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i7.GSR = "DISABLED";
    FD1P3AX tdata_i0_i6 (.D(tx_buf[30]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i6.GSR = "DISABLED";
    FD1P3AX tdata_i0_i5 (.D(tx_buf[29]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i5.GSR = "DISABLED";
    FD1P3AX tdata_i0_i4 (.D(tx_buf[28]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i4.GSR = "DISABLED";
    FD1P3AX tdata_i0_i3 (.D(tx_buf[27]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i3.GSR = "DISABLED";
    LUT4 i1_2_lut_rep_54 (.A(cnt[0]), .B(cnt[1]), .Z(n3703)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(452[18:29])
    defparam i1_2_lut_rep_54.init = 16'heeee;
    LUT4 i1_2_lut_4_lut_4_lut (.A(cnt[0]), .B(cnt[1]), .C(cnt[2]), .D(n3691), 
         .Z(cnt_2__N_303[0])) /* synthesis lut_function=(!(A+!(B (D)+!B (C (D))))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(452[18:29])
    defparam i1_2_lut_4_lut_4_lut.init = 16'h5400;
    FD1P3AX tdata_i0_i2 (.D(tx_buf[26]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i2.GSR = "DISABLED";
    FD1P3AX tdata_i0_i1 (.D(tx_buf[25]), .SP(clk_c_enable_116), .CK(clk_c), 
            .Q(tdata[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tdata_i0_i1.GSR = "DISABLED";
    LUT4 mux_88_i19_3_lut (.A(wr_data[18]), .B(tx_buf[10]), .C(n308), 
         .Z(n327)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i19_3_lut.init = 16'hcaca;
    LUT4 mux_88_i20_3_lut (.A(wr_data[19]), .B(tx_buf[11]), .C(n308), 
         .Z(n328)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i20_3_lut.init = 16'hcaca;
    LUT4 mux_88_i21_3_lut (.A(wr_data[20]), .B(tx_buf[12]), .C(n308), 
         .Z(n329)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i21_3_lut.init = 16'hcaca;
    LUT4 mux_88_i22_3_lut (.A(wr_data[21]), .B(tx_buf[13]), .C(n308), 
         .Z(n330)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i22_3_lut.init = 16'hcaca;
    LUT4 mux_88_i23_3_lut (.A(wr_data[22]), .B(tx_buf[14]), .C(n308), 
         .Z(n331)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i23_3_lut.init = 16'hcaca;
    FD1P3IX tx_buf_i0_i7 (.D(wr_data[7]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[7])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i7.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i6 (.D(wr_data[6]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[6])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i6.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i5 (.D(wr_data[5]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[5])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i5.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i4 (.D(wr_data[4]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[4])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i4.GSR = "ENABLED";
    LUT4 mux_88_i24_3_lut (.A(wr_data[23]), .B(tx_buf[15]), .C(n308), 
         .Z(n332)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i24_3_lut.init = 16'hcaca;
    FD1P3IX tx_buf_i0_i3 (.D(wr_data[3]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[3])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i3.GSR = "ENABLED";
    FD1P3IX tx_buf_i0_i2 (.D(wr_data[2]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i2.GSR = "ENABLED";
    LUT4 mux_88_i25_3_lut (.A(wr_data[24]), .B(tx_buf[16]), .C(n308), 
         .Z(n333)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i25_3_lut.init = 16'hcaca;
    FD1P3IX tx_buf_i0_i1 (.D(wr_data[1]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i1.GSR = "ENABLED";
    FD1P3AX cnt_i1 (.D(cnt_2__N_303[1]), .SP(clk_c_enable_146), .CK(clk_c), 
            .Q(cnt[1])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam cnt_i1.GSR = "ENABLED";
    FD1P3AX cnt_i2 (.D(cnt_2__N_303[2]), .SP(clk_c_enable_146), .CK(clk_c), 
            .Q(cnt[2])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam cnt_i2.GSR = "ENABLED";
    LUT4 mux_88_i26_3_lut (.A(wr_data[25]), .B(tx_buf[17]), .C(n308), 
         .Z(n334)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i26_3_lut.init = 16'hcaca;
    FD1P3IX tx_buf_i0_i0 (.D(wr_data[0]), .SP(clk_c_enable_193), .CD(n1809), 
            .CK(clk_c), .Q(tx_buf[0])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i0.GSR = "ENABLED";
    FD1S3AY start_30 (.D(n308), .CK(clk_c), .Q(start));   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam start_30.GSR = "ENABLED";
    LUT4 mux_88_i27_3_lut (.A(wr_data[26]), .B(tx_buf[18]), .C(n308), 
         .Z(n335)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i27_3_lut.init = 16'hcaca;
    FD1P3AX tx_buf_i0_i8 (.D(n317), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[8])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i8.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i9 (.D(n318), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[9])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i9.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i10 (.D(n319), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[10])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i10.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i11 (.D(n320), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[11])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i11.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i12 (.D(n321), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[12])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i12.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i13 (.D(n322), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[13])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i13.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i14 (.D(n323), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[14])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i14.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i15 (.D(n324), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[15])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i15.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i16 (.D(n325), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[16])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i16.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i17 (.D(n326), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[17])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i17.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i18 (.D(n327), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[18])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i18.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i19 (.D(n328), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[19])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i19.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i20 (.D(n329), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[20])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i20.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i21 (.D(n330), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[21])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i21.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i22 (.D(n331), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[22])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i22.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i23 (.D(n332), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[23])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i23.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i24 (.D(n333), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[24])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i24.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i25 (.D(n334), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[25])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i25.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i26 (.D(n335), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[26])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i26.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i27 (.D(n336), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[27])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i27.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i28 (.D(n337), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[28])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i28.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i29 (.D(n338), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[29])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i29.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i30 (.D(n339), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[30])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i30.GSR = "ENABLED";
    FD1P3AX tx_buf_i0_i31 (.D(n340), .SP(clk_c_enable_193), .CK(clk_c), 
            .Q(tx_buf[31])) /* synthesis LSE_LINE_FILE_ID=4, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=57, LSE_RLINE=68 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam tx_buf_i0_i31.GSR = "ENABLED";
    LUT4 i99_2_lut (.A(n308), .B(rst_n), .Z(clk_c_enable_116)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam i99_2_lut.init = 16'h8888;
    LUT4 i1_4_lut (.A(start), .B(tx_buf_31__N_412), .C(n3348), .D(r_shift_12__N_666[12]), 
         .Z(n308)) /* synthesis lut_function=(!(A+!(B (C+!(D))))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam i1_4_lut.init = 16'h4044;
    LUT4 i1_4_lut_adj_19 (.A(r_shift_cnt[0]), .B(r_shift_cnt[3]), .C(r_shift_cnt[1]), 
         .D(r_shift_cnt[2]), .Z(n3348)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam i1_4_lut_adj_19.init = 16'h0040;
    LUT4 i262_4_lut (.A(start), .B(wr), .C(tx_buf_31__N_412), .D(nstate[1]), 
         .Z(clk_c_enable_193)) /* synthesis lut_function=(!(A ((C)+!B)+!A (B (C (D))+!B ((D)+!C)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam i262_4_lut.init = 16'h0c5c;
    LUT4 mux_88_i28_3_lut (.A(wr_data[27]), .B(tx_buf[19]), .C(n308), 
         .Z(n336)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i28_3_lut.init = 16'hcaca;
    LUT4 i1309_2_lut (.A(clk_c_enable_193), .B(n308), .Z(n1809)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(462[10] 480[8])
    defparam i1309_2_lut.init = 16'h8888;
    LUT4 mux_88_i29_3_lut (.A(wr_data[28]), .B(tx_buf[20]), .C(n308), 
         .Z(n337)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i29_3_lut.init = 16'hcaca;
    LUT4 mux_88_i30_3_lut (.A(wr_data[29]), .B(tx_buf[21]), .C(n308), 
         .Z(n338)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i30_3_lut.init = 16'hcaca;
    LUT4 mux_88_i31_3_lut (.A(wr_data[30]), .B(tx_buf[22]), .C(n308), 
         .Z(n339)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i31_3_lut.init = 16'hcaca;
    LUT4 mux_88_i32_3_lut (.A(wr_data[31]), .B(tx_buf[23]), .C(n308), 
         .Z(n340)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i32_3_lut.init = 16'hcaca;
    LUT4 i2879_2_lut (.A(cnt[2]), .B(cnt[1]), .Z(tx_buf_31__N_412)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2879_2_lut.init = 16'heeee;
    LUT4 i1_3_lut_4_lut (.A(r_shift_12__N_666[12]), .B(n3699), .C(tx_buf_31__N_412), 
         .D(wr), .Z(clk_c_enable_146)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A (C+!(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(477[9] 479[12])
    defparam i1_3_lut_4_lut.init = 16'h2f22;
    LUT4 mux_88_i9_3_lut (.A(wr_data[8]), .B(tx_buf[0]), .C(n308), .Z(n317)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i9_3_lut.init = 16'hcaca;
    LUT4 mux_88_i10_3_lut (.A(wr_data[9]), .B(tx_buf[1]), .C(n308), .Z(n318)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i10_3_lut.init = 16'hcaca;
    LUT4 mux_88_i11_3_lut (.A(wr_data[10]), .B(tx_buf[2]), .C(n308), .Z(n319)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i11_3_lut.init = 16'hcaca;
    LUT4 i2957_3_lut_4_lut (.A(r_shift_12__N_666[12]), .B(n3699), .C(cnt[2]), 
         .D(n3703), .Z(cnt_2__N_303[2])) /* synthesis lut_function=((B+(C (D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(477[9] 479[12])
    defparam i2957_3_lut_4_lut.init = 16'hfddd;
    LUT4 mux_88_i12_3_lut (.A(wr_data[11]), .B(tx_buf[3]), .C(n308), .Z(n320)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i12_3_lut.init = 16'hcaca;
    LUT4 mux_88_i13_3_lut (.A(wr_data[12]), .B(tx_buf[4]), .C(n308), .Z(n321)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(471[14] 474[12])
    defparam mux_88_i13_3_lut.init = 16'hcaca;
    PFUMX i3010 (.BLUT(n3711), .ALUT(n3712), .C0(cnt[1]), .Z(cnt_2__N_303[1]));
    Debug_core_uart_tx Debug_core_uart_tx_uut (.\r_shift_12__N_666[12] (r_shift_12__N_666[12]), 
            .clk_c(clk_c), .\nstate[1] (nstate[1]), .tx_c(tx_c), .start(start), 
            .r_shift_cnt({r_shift_cnt}), .n3699(n3699), .GND_net(GND_net), 
            .tdata({tdata}), .n3691(n3691)) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(507[3] 515[2])
    Debug_core_uart_rx Debug_core_uart_rx_uut (.clk_c(clk_c), .rx_c(rx_c), 
            .rx_data({rx_data}), .GND_net(GND_net), .n3707(n3707), .\cnt[1] (cnt_adj_691[1]), 
            .\cnt[0] (cnt_adj_691[0]), .\cnt_2__N_615[1] (cnt_2__N_615[1]), 
            .\cnt_2__N_615[0] (cnt_2__N_615[0])) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(486[3] 492[2])
    Debug_core_DecodeUart Debug_core_DecodeUart_uut (.cnt({Open_0, Open_1, 
            cnt_adj_691[0]}), .n3707(n3707), .cmd_data({cmd_data}), .clk_c(clk_c), 
            .rx_data({rx_data}), .cmd({cmd}), .rst_n(rst_n), .n3702(n3702), 
            .valid_o(valid_o), .clk_c_enable_102(clk_c_enable_102), .\cnt[1] (cnt_adj_691[1]), 
            .\cnt_2__N_615[1] (cnt_2__N_615[1]), .n3971(n3971), .\cnt_2__N_615[0] (cnt_2__N_615[0])) /* synthesis syn_module_defined=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(494[23] 502[2])
    
endmodule
//
// Verilog Description of module Debug_core_uart_tx
//

module Debug_core_uart_tx (\r_shift_12__N_666[12] , clk_c, \nstate[1] , 
            tx_c, start, r_shift_cnt, n3699, GND_net, tdata, n3691) /* synthesis syn_module_defined=1 */ ;
    output \r_shift_12__N_666[12] ;
    input clk_c;
    output \nstate[1] ;
    output tx_c;
    input start;
    output [3:0]r_shift_cnt;
    output n3699;
    input GND_net;
    input [7:0]tdata;
    output n3691;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    
    wire clk_c_enable_169;
    wire [12:0]r_shift_12__N_639;
    
    wire r_tx_order_buf, n3709, n3695, n3969, n1825;
    wire [3:0]n21;
    
    wire n1611, n3700;
    wire [6:0]r_hold_cnt;   // f:/home/mini-step-fpga/prj/template/debug_core.v(234[34:44])
    
    wire n3718, n3717;
    wire [6:0]n33;
    
    wire n3705, n3449;
    wire [12:0]r_shift;   // f:/home/mini-step-fpga/prj/template/debug_core.v(233[18:25])
    wire [12:0]r_shift_12__N_666;
    
    wire clk_c_enable_168, n3968, n3719, n3706, n3004, n3005, n3371, 
        n3006;
    
    FD1S3AX cstate_i1 (.D(\nstate[1] ), .CK(clk_c), .Q(\r_shift_12__N_666[12] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(262[13:30])
    defparam cstate_i1.GSR = "ENABLED";
    FD1P3AY r_shift_i1 (.D(r_shift_12__N_639[0]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(tx_c)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i1.GSR = "ENABLED";
    FD1S3AX r_tx_order_buf_57 (.D(start), .CK(clk_c), .Q(r_tx_order_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(250[9] 253[12])
    defparam r_tx_order_buf_57.GSR = "ENABLED";
    LUT4 cstate_1__I_0_i4_1_lut_rep_60 (.A(\r_shift_12__N_666[12] ), .Z(n3709)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(297[16:30])
    defparam cstate_1__I_0_i4_1_lut_rep_60.init = 16'h5555;
    LUT4 r_shift_cnt_0__bdd_4_lut (.A(r_shift_cnt[0]), .B(r_shift_cnt[1]), 
         .C(r_shift_cnt[2]), .D(n3695), .Z(n3969)) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;
    defparam r_shift_cnt_0__bdd_4_lut.init = 16'h78f0;
    LUT4 i2_3_lut_3_lut (.A(\r_shift_12__N_666[12] ), .B(start), .C(r_tx_order_buf), 
         .Z(n1825)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(297[16:30])
    defparam i2_3_lut_3_lut.init = 16'h0404;
    FD1S3IX r_shift_cnt_321__i0 (.D(n21[0]), .CK(clk_c), .CD(n3709), .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_321__i0.GSR = "ENABLED";
    LUT4 i2478_2_lut_3_lut_4_lut_4_lut_then_4_lut (.A(n1611), .B(n3700), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n3718)) /* synthesis lut_function=(A (B (D)+!B !(C (D)+!C !(D)))+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam i2478_2_lut_3_lut_4_lut_4_lut_then_4_lut.init = 16'hdf21;
    LUT4 i2478_2_lut_3_lut_4_lut_4_lut_else_4_lut (.A(n1611), .B(n3700), 
         .C(r_hold_cnt[1]), .D(r_shift_cnt[1]), .Z(n3717)) /* synthesis lut_function=(A (D)+!A (B (D)+!B ((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam i2478_2_lut_3_lut_4_lut_4_lut_else_4_lut.init = 16'hff01;
    FD1S3IX r_hold_cnt_326__i6 (.D(n33[6]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i6.GSR = "ENABLED";
    LUT4 i1_2_lut_rep_56 (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .Z(n3705)) /* synthesis lut_function=(A+!(B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_56.init = 16'hbbbb;
    LUT4 i2916_4_lut (.A(r_hold_cnt[2]), .B(r_hold_cnt[5]), .C(r_hold_cnt[0]), 
         .D(r_hold_cnt[6]), .Z(n3449)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2916_4_lut.init = 16'h8000;
    FD1P3JX r_shift_i12 (.D(r_shift_12__N_666[11]), .SP(clk_c_enable_169), 
            .PD(n1825), .CK(clk_c), .Q(r_shift[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i12.GSR = "ENABLED";
    FD1P3JX r_shift_i11 (.D(r_shift_12__N_666[10]), .SP(clk_c_enable_169), 
            .PD(n1825), .CK(clk_c), .Q(r_shift[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i11.GSR = "ENABLED";
    LUT4 i2_3_lut_rep_50_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), 
         .C(r_shift_cnt[1]), .D(r_shift_cnt[0]), .Z(n3699)) /* synthesis lut_function=(A+(((D)+!C)+!B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(305[10:27])
    defparam i2_3_lut_rep_50_4_lut.init = 16'hffbf;
    FD1S3IX r_hold_cnt_326__i5 (.D(n33[5]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i5.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_326__i4 (.D(n33[4]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i4.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_326__i3 (.D(n33[3]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i3.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_326__i2 (.D(n33[2]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i2.GSR = "ENABLED";
    FD1S3IX r_hold_cnt_326__i1 (.D(n33[1]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i1.GSR = "ENABLED";
    LUT4 i2961_3_lut_rep_43 (.A(n3700), .B(r_hold_cnt[1]), .C(n1611), 
         .Z(clk_c_enable_168)) /* synthesis lut_function=(!(A+!(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(315[10:40])
    defparam i2961_3_lut_rep_43.init = 16'h4141;
    FD1S3IX r_hold_cnt_326__i0 (.D(n33[0]), .CK(clk_c), .CD(clk_c_enable_169), 
            .Q(r_hold_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326__i0.GSR = "ENABLED";
    FD1P3AY r_shift_i2 (.D(r_shift_12__N_639[1]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i2.GSR = "ENABLED";
    LUT4 i2_3_lut_rep_62 (.A(n1611), .B(n3700), .C(r_hold_cnt[1]), .Z(n3968)) /* synthesis lut_function=(A+(B+(C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(306[10:37])
    defparam i2_3_lut_rep_62.init = 16'hfefe;
    FD1P3AY r_shift_i3 (.D(r_shift_12__N_639[2]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i3.GSR = "ENABLED";
    FD1P3AY r_shift_i4 (.D(r_shift_12__N_639[3]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i4.GSR = "ENABLED";
    FD1P3AY r_shift_i5 (.D(r_shift_12__N_639[4]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i5.GSR = "ENABLED";
    FD1P3AY r_shift_i6 (.D(r_shift_12__N_639[5]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i6.GSR = "ENABLED";
    FD1P3AY r_shift_i7 (.D(r_shift_12__N_639[6]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i7.GSR = "ENABLED";
    FD1P3AY r_shift_i8 (.D(r_shift_12__N_639[7]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i8.GSR = "ENABLED";
    FD1P3AY r_shift_i9 (.D(r_shift_12__N_639[8]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i9.GSR = "ENABLED";
    FD1P3JX r_shift_i10 (.D(r_shift[10]), .SP(clk_c_enable_168), .PD(n3709), 
            .CK(clk_c), .Q(r_shift[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i10.GSR = "ENABLED";
    FD1P3AY r_shift_i13 (.D(r_shift_12__N_639[12]), .SP(clk_c_enable_169), 
            .CK(clk_c), .Q(r_shift[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=507, LSE_RLINE=515 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(296[9] 330[12])
    defparam r_shift_i13.GSR = "ENABLED";
    LUT4 i2950_2_lut_4_lut (.A(n3700), .B(r_hold_cnt[1]), .C(n1611), .D(\r_shift_12__N_666[12] ), 
         .Z(clk_c_enable_169)) /* synthesis lut_function=(!(A (D)+!A !(B (C+!(D))+!B !(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(315[10:40])
    defparam i2950_2_lut_4_lut.init = 16'h41ff;
    LUT4 i2_3_lut_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[3]), .C(r_shift_cnt[1]), 
         .D(r_shift_cnt[0]), .Z(n1611)) /* synthesis lut_function=(A+((C+!(D))+!B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(305[10:27])
    defparam i2_3_lut_4_lut.init = 16'hfbff;
    FD1S3IX r_shift_cnt_321__i1 (.D(n3719), .CK(clk_c), .CD(n3709), .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_321__i1.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_321__i2 (.D(n3969), .CK(clk_c), .CD(n3709), .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_321__i2.GSR = "ENABLED";
    FD1S3IX r_shift_cnt_321__i3 (.D(n21[3]), .CK(clk_c), .CD(n3709), .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam r_shift_cnt_321__i3.GSR = "ENABLED";
    LUT4 start_I_0_2_lut_rep_57 (.A(start), .B(r_tx_order_buf), .Z(n3706)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(241[29:54])
    defparam start_I_0_2_lut_rep_57.init = 16'h2222;
    LUT4 i2470_2_lut_3_lut_4_lut (.A(n1611), .B(n3695), .C(n3968), .D(r_shift_cnt[0]), 
         .Z(n21[0])) /* synthesis lut_function=(!(A (B (C (D))+!B !(C (D)))+!A !(C (D)))) */ ;
    defparam i2470_2_lut_3_lut_4_lut.init = 16'h7888;
    LUT4 i1958_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_666[12] ), 
         .D(r_shift[1]), .Z(r_shift_12__N_639[0])) /* synthesis lut_function=(A (B ((D)+!C)+!B (C (D)))+!A ((D)+!C)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(241[29:54])
    defparam i1958_3_lut_4_lut.init = 16'hfd0d;
    CCU2D r_hold_cnt_326_add_4_3 (.A0(r_hold_cnt[1]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[2]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3004), .COUT(n3005), .S0(n33[1]), .S1(n33[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326_add_4_3.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_3.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_3.INJECT1_0 = "NO";
    defparam r_hold_cnt_326_add_4_3.INJECT1_1 = "NO";
    LUT4 mux_631_i1_3_lut_4_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_666[12] ), 
         .D(n3699), .Z(\nstate[1] )) /* synthesis lut_function=(A (B (C (D))+!B ((D)+!C))+!A (C (D))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(241[29:54])
    defparam mux_631_i1_3_lut_4_lut.init = 16'hf202;
    LUT4 i2019_2_lut_3_lut (.A(start), .B(r_tx_order_buf), .C(\r_shift_12__N_666[12] ), 
         .Z(r_shift_12__N_639[12])) /* synthesis lut_function=(A ((C)+!B)+!A (C)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(241[29:54])
    defparam i2019_2_lut_3_lut.init = 16'hf2f2;
    LUT4 i2008_2_lut (.A(r_shift[12]), .B(\r_shift_12__N_666[12] ), .Z(r_shift_12__N_666[11])) /* synthesis lut_function=(A (B)) */ ;
    defparam i2008_2_lut.init = 16'h8888;
    LUT4 i1985_2_lut (.A(r_shift[11]), .B(\r_shift_12__N_666[12] ), .Z(r_shift_12__N_666[10])) /* synthesis lut_function=(A (B)) */ ;
    defparam i1985_2_lut.init = 16'h8888;
    LUT4 i2492_3_lut (.A(r_shift_cnt[3]), .B(n3371), .C(n3968), .Z(n21[3])) /* synthesis lut_function=(!(A (B)+!A !(B (C)+!B !(C)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam i2492_3_lut.init = 16'h6363;
    LUT4 i3_4_lut (.A(r_shift_cnt[2]), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(n3695), .Z(n3371)) /* synthesis lut_function=(A (B (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(314[10] 322[8])
    defparam i3_4_lut.init = 16'h8000;
    LUT4 r_shift_12__I_0_i2_4_lut (.A(tdata[0]), .B(r_shift[2]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[1])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i2_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i3_4_lut (.A(tdata[1]), .B(r_shift[3]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[2])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i3_4_lut.init = 16'hcacf;
    CCU2D r_hold_cnt_326_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3004), .S1(n33[0]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326_add_4_1.INIT0 = 16'hF000;
    defparam r_hold_cnt_326_add_4_1.INIT1 = 16'h0555;
    defparam r_hold_cnt_326_add_4_1.INJECT1_0 = "NO";
    defparam r_hold_cnt_326_add_4_1.INJECT1_1 = "NO";
    LUT4 r_shift_12__I_0_i4_4_lut (.A(tdata[2]), .B(r_shift[4]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[3])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i4_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i5_4_lut (.A(tdata[3]), .B(r_shift[5]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[4])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i5_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i6_4_lut (.A(tdata[4]), .B(r_shift[6]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[5])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i6_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i7_4_lut (.A(tdata[5]), .B(r_shift[7]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[6])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i7_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i8_4_lut (.A(tdata[6]), .B(r_shift[8]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[7])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i8_4_lut.init = 16'hcacf;
    LUT4 r_shift_12__I_0_i9_4_lut (.A(tdata[7]), .B(r_shift[9]), .C(\r_shift_12__N_666[12] ), 
         .D(n3706), .Z(r_shift_12__N_639[8])) /* synthesis lut_function=(A (B+!(C))+!A (B (C+!(D))+!B !(C+(D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(303[18] 329[16])
    defparam r_shift_12__I_0_i9_4_lut.init = 16'hcacf;
    CCU2D r_hold_cnt_326_add_4_5 (.A0(r_hold_cnt[3]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[4]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3005), .COUT(n3006), .S0(n33[3]), .S1(n33[4]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326_add_4_5.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_5.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_5.INJECT1_0 = "NO";
    defparam r_hold_cnt_326_add_4_5.INJECT1_1 = "NO";
    CCU2D r_hold_cnt_326_add_4_7 (.A0(r_hold_cnt[5]), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_hold_cnt[6]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .CIN(n3006), .S0(n33[5]), .S1(n33[6]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(321[26:43])
    defparam r_hold_cnt_326_add_4_7.INIT0 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_7.INIT1 = 16'hfaaa;
    defparam r_hold_cnt_326_add_4_7.INJECT1_0 = "NO";
    defparam r_hold_cnt_326_add_4_7.INJECT1_1 = "NO";
    LUT4 i1_2_lut_rep_42_4_lut (.A(n3705), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .D(\r_shift_12__N_666[12] ), .Z(n3691)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(305[10:27])
    defparam i1_2_lut_rep_42_4_lut.init = 16'h1000;
    LUT4 i2_3_lut_rep_51 (.A(n3449), .B(r_hold_cnt[3]), .C(r_hold_cnt[4]), 
         .Z(n3700)) /* synthesis lut_function=((B+(C))+!A) */ ;
    defparam i2_3_lut_rep_51.init = 16'hfdfd;
    LUT4 i1_2_lut_rep_46_4_lut (.A(n3449), .B(r_hold_cnt[3]), .C(r_hold_cnt[4]), 
         .D(r_hold_cnt[1]), .Z(n3695)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
    defparam i1_2_lut_rep_46_4_lut.init = 16'h0200;
    PFUMX i3014 (.BLUT(n3717), .ALUT(n3718), .C0(r_shift_cnt[0]), .Z(n3719));
    
endmodule
//
// Verilog Description of module Debug_core_uart_rx
//

module Debug_core_uart_rx (clk_c, rx_c, rx_data, GND_net, n3707, \cnt[1] , 
            \cnt[0] , \cnt_2__N_615[1] , \cnt_2__N_615[0] ) /* synthesis syn_module_defined=1 */ ;
    input clk_c;
    input rx_c;
    output [7:0]rx_data;
    input GND_net;
    output n3707;
    input \cnt[1] ;
    input \cnt[0] ;
    output \cnt_2__N_615[1] ;
    output \cnt_2__N_615[0] ;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    wire [2:0]n736;
    
    wire n1814;
    wire [3:0]r_shift_cnt;   // f:/home/mini-step-fpga/prj/template/debug_core.v(69[17:28])
    
    wire clk_c_enable_22, n3094;
    wire [6:0]r_sample_cnt;   // f:/home/mini-step-fpga/prj/template/debug_core.v(62[34:46])
    
    wire clk_c_enable_159, n1803;
    wire [6:0]n33;
    wire [9:0]r_shift;   // f:/home/mini-step-fpga/prj/template/debug_core.v(70[17:24])
    
    wire clk_c_enable_156;
    wire [3:0]n21;
    
    wire clk_c_enable_154;
    wire [1:0]nstate_1__N_453;
    
    wire r_uart_rx_falling_N_527;
    wire [1:0]nstate_1__N_451;
    
    wire n1146, n1159, busy_f, busy, r_uart_rx_buf, n13, n3423, 
        n3670, n3051, n6, n3672, n3001, n3002, n3698, n3000, 
        n9;
    
    LUT4 i2953_2_lut_3_lut (.A(n736[0]), .B(n736[2]), .C(n736[1]), .Z(n1814)) /* synthesis lut_function=(!(A ((C)+!B)+!A (C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(168[18] 180[16])
    defparam i2953_2_lut_3_lut.init = 16'h0d0d;
    FD1P3IX r_shift_cnt_322__i0 (.D(n3094), .SP(clk_c_enable_22), .CD(n1814), 
            .CK(clk_c), .Q(r_shift_cnt[0]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam r_shift_cnt_322__i0.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i1 (.D(n33[1]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[1])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i1.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i2 (.D(n33[2]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[2])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i2.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i3 (.D(n33[3]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[3])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i3.GSR = "ENABLED";
    FD1P3JX r_shift__0__i3 (.D(r_shift[4]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[3]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i3.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i4 (.D(n33[4]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[4])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i4.GSR = "ENABLED";
    FD1P3JX r_shift__0__i4 (.D(r_shift[5]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[4]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i4.GSR = "ENABLED";
    FD1P3JX r_shift__0__i5 (.D(r_shift[6]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[5]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i5.GSR = "ENABLED";
    FD1P3JX r_shift__0__i6 (.D(r_shift[7]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[6]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i6.GSR = "ENABLED";
    FD1P3JX r_shift__0__i7 (.D(r_shift[8]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[7]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i7.GSR = "ENABLED";
    FD1P3JX r_shift__0__i8 (.D(r_shift[9]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[8]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i8.GSR = "ENABLED";
    FD1P3JX r_shift__0__i9 (.D(rx_c), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[9]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i9.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_322__i1 (.D(n21[1]), .SP(clk_c_enable_22), .CD(n1814), 
            .CK(clk_c), .Q(r_shift_cnt[1]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam r_shift_cnt_322__i1.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i0 (.D(r_shift[1]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i0.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_322__i2 (.D(n21[2]), .SP(clk_c_enable_22), .CD(n1814), 
            .CK(clk_c), .Q(r_shift_cnt[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam r_shift_cnt_322__i2.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i5 (.D(n33[5]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[5])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i5.GSR = "ENABLED";
    FD1P3IX r_sample_cnt_324__i6 (.D(n33[6]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[6])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i6.GSR = "ENABLED";
    FD1P3IX r_shift_cnt_322__i3 (.D(n21[3]), .SP(clk_c_enable_22), .CD(n1814), 
            .CK(clk_c), .Q(r_shift_cnt[3]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam r_shift_cnt_322__i3.GSR = "ENABLED";
    FD1S3AX r_uart_rx_falling_62 (.D(r_uart_rx_falling_N_527), .CK(clk_c), 
            .Q(nstate_1__N_453[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_falling_62.GSR = "ENABLED";
    FD1S3IX cstate_FSM_i2 (.D(n736[1]), .CK(clk_c), .CD(nstate_1__N_451[0]), 
            .Q(n736[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i2.GSR = "ENABLED";
    FD1S3AX cstate_FSM_i1 (.D(n1146), .CK(clk_c), .Q(n736[1]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i1.GSR = "ENABLED";
    LUT4 i663_2_lut (.A(n736[0]), .B(nstate_1__N_453[0]), .Z(n1159)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(111[9] 126[17])
    defparam i663_2_lut.init = 16'h2222;
    FD1S3AX busy_f_70 (.D(busy), .CK(clk_c), .Q(busy_f)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(191[8] 193[6])
    defparam busy_f_70.GSR = "ENABLED";
    FD1S3AX r_uart_rx_buf_61 (.D(rx_c), .CK(clk_c), .Q(r_uart_rx_buf)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(90[9] 93[12])
    defparam r_uart_rx_buf_61.GSR = "ENABLED";
    FD1S3JX cstate_FSM_i0 (.D(n1159), .CK(clk_c), .PD(n736[2]), .Q(n736[0]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(111[9] 126[17])
    defparam cstate_FSM_i0.GSR = "ENABLED";
    LUT4 i266_3_lut_4_lut (.A(n736[0]), .B(n736[2]), .C(n736[1]), .D(n13), 
         .Z(clk_c_enable_156)) /* synthesis lut_function=(!(A (B (C (D))+!B ((D)+!C))+!A (C (D)))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(168[18] 180[16])
    defparam i266_3_lut_4_lut.init = 16'h0dfd;
    LUT4 i2890_2_lut (.A(nstate_1__N_453[0]), .B(n736[1]), .Z(n3423)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2890_2_lut.init = 16'heeee;
    LUT4 n3051_bdd_4_lut_3073 (.A(r_sample_cnt[3]), .B(r_sample_cnt[6]), 
         .C(r_sample_cnt[4]), .D(r_sample_cnt[2]), .Z(n3670)) /* synthesis lut_function=(!(A+((C+!(D))+!B))) */ ;
    defparam n3051_bdd_4_lut_3073.init = 16'h0400;
    FD1P3JX r_shift__0__i2 (.D(r_shift[3]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i2.GSR = "ENABLED";
    LUT4 i4_4_lut (.A(r_sample_cnt[4]), .B(n3051), .C(r_sample_cnt[6]), 
         .D(n6), .Z(n13)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(151[8:38])
    defparam i4_4_lut.init = 16'hfffd;
    FD1P3AX r_rx_data_i0_i7 (.D(r_shift[8]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i7.GSR = "ENABLED";
    LUT4 n3670_bdd_4_lut (.A(n3670), .B(n3051), .C(n3672), .D(n736[1]), 
         .Z(n1803)) /* synthesis lut_function=(!(A (B ((D)+!C)+!B !(C+(D)))+!A ((D)+!C))) */ ;
    defparam n3670_bdd_4_lut.init = 16'h22f0;
    FD1P3AX r_rx_data_i0_i6 (.D(r_shift[7]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i6.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i5 (.D(r_shift[6]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i5.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i4 (.D(r_shift[5]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i4.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i3 (.D(r_shift[4]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i3.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i2 (.D(r_shift[3]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i2.GSR = "ENABLED";
    FD1P3AX r_rx_data_i0_i1 (.D(r_shift[2]), .SP(clk_c_enable_154), .CK(clk_c), 
            .Q(rx_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=3, LSE_RCOL=2, LSE_LLINE=486, LSE_RLINE=492 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_rx_data_i0_i1.GSR = "ENABLED";
    FD1P3JX r_shift__0__i1 (.D(r_shift[2]), .SP(clk_c_enable_156), .PD(n1814), 
            .CK(clk_c), .Q(r_shift[1]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(141[9] 181[12])
    defparam r_shift__0__i1.GSR = "ENABLED";
    LUT4 i1_2_lut (.A(r_sample_cnt[3]), .B(r_sample_cnt[2]), .Z(n6)) /* synthesis lut_function=(A+(B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(151[8:38])
    defparam i1_2_lut.init = 16'heeee;
    FD1P3IX r_sample_cnt_324__i0 (.D(n33[0]), .SP(clk_c_enable_159), .CD(n1803), 
            .CK(clk_c), .Q(r_sample_cnt[0])) /* synthesis syn_use_carry_chain=1 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324__i0.GSR = "ENABLED";
    LUT4 n3051_bdd_3_lut (.A(n736[0]), .B(n736[2]), .C(nstate_1__N_453[0]), 
         .Z(n3672)) /* synthesis lut_function=(!(A (B+!(C))+!A (B))) */ ;
    defparam n3051_bdd_3_lut.init = 16'h3131;
    CCU2D r_sample_cnt_324_add_4_5 (.A0(r_sample_cnt[3]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[4]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3001), .COUT(n3002), .S0(n33[3]), 
          .S1(n33[4]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324_add_4_5.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_5.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_5.INJECT1_0 = "NO";
    defparam r_sample_cnt_324_add_4_5.INJECT1_1 = "NO";
    LUT4 i128_2_lut (.A(n736[2]), .B(n736[1]), .Z(clk_c_enable_154)) /* synthesis lut_function=(!((B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(156[18] 180[16])
    defparam i128_2_lut.init = 16'h2222;
    LUT4 i2464_3_lut_4_lut (.A(r_shift_cnt[1]), .B(n3698), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[3]), .Z(n21[3])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam i2464_3_lut_4_lut.init = 16'h7f80;
    LUT4 i1_2_lut_adj_18 (.A(n13), .B(r_shift_cnt[0]), .Z(n3094)) /* synthesis lut_function=(A (B)+!A !(B)) */ ;
    defparam i1_2_lut_adj_18.init = 16'h9999;
    LUT4 i2947_3_lut (.A(r_sample_cnt[1]), .B(r_sample_cnt[5]), .C(r_sample_cnt[0]), 
         .Z(n3051)) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i2947_3_lut.init = 16'h7f7f;
    LUT4 busy_N_521_I_0_2_lut_rep_58 (.A(n736[0]), .B(busy_f), .Z(n3707)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(186[21:37])
    defparam busy_N_521_I_0_2_lut_rep_58.init = 16'h8888;
    LUT4 i380_2_lut_3_lut_4_lut (.A(n736[0]), .B(busy_f), .C(\cnt[1] ), 
         .D(\cnt[0] ), .Z(\cnt_2__N_615[1] )) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(186[21:37])
    defparam i380_2_lut_3_lut_4_lut.init = 16'h78f0;
    LUT4 i372_2_lut_3_lut (.A(n736[0]), .B(busy_f), .C(\cnt[0] ), .Z(\cnt_2__N_615[0] )) /* synthesis lut_function=(!(A (B (C)+!B !(C))+!A !(C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(186[21:37])
    defparam i372_2_lut_3_lut.init = 16'h7878;
    CCU2D r_sample_cnt_324_add_4_7 (.A0(r_sample_cnt[5]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[6]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3002), .S0(n33[5]), .S1(n33[6]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324_add_4_7.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_7.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_7.INJECT1_0 = "NO";
    defparam r_sample_cnt_324_add_4_7.INJECT1_1 = "NO";
    LUT4 i2_4_lut (.A(r_shift_cnt[1]), .B(r_shift_cnt[0]), .C(r_shift_cnt[3]), 
         .D(r_shift_cnt[2]), .Z(nstate_1__N_451[0])) /* synthesis lut_function=((B+((D)+!C))+!A) */ ;
    defparam i2_4_lut.init = 16'hffdf;
    LUT4 i651_4_lut (.A(n736[1]), .B(nstate_1__N_453[0]), .C(nstate_1__N_451[0]), 
         .D(n736[0]), .Z(n1146)) /* synthesis lut_function=(A (B (C+(D))+!B (C))+!A (B (D))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(111[9] 126[17])
    defparam i651_4_lut.init = 16'heca0;
    LUT4 i2444_2_lut_rep_49 (.A(n13), .B(r_shift_cnt[0]), .Z(n3698)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam i2444_2_lut_rep_49.init = 16'h4444;
    LUT4 i2450_2_lut_3_lut (.A(n13), .B(r_shift_cnt[0]), .C(r_shift_cnt[1]), 
         .Z(n21[1])) /* synthesis lut_function=(A (C)+!A !(B (C)+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam i2450_2_lut_3_lut.init = 16'hb4b4;
    LUT4 busy_I_0_1_lut (.A(n736[0]), .Z(busy)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(76[19:48])
    defparam busy_I_0_1_lut.init = 16'h5555;
    LUT4 i2457_2_lut_3_lut_4_lut (.A(n13), .B(r_shift_cnt[0]), .C(r_shift_cnt[2]), 
         .D(r_shift_cnt[1]), .Z(n21[2])) /* synthesis lut_function=(A (C)+!A !(B (C (D)+!C !(D))+!B !(C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(146[36:54])
    defparam i2457_2_lut_3_lut_4_lut.init = 16'hb4f0;
    CCU2D r_sample_cnt_324_add_4_3 (.A0(r_sample_cnt[1]), .B0(GND_net), 
          .C0(GND_net), .D0(GND_net), .A1(r_sample_cnt[2]), .B1(GND_net), 
          .C1(GND_net), .D1(GND_net), .CIN(n3000), .COUT(n3001), .S0(n33[1]), 
          .S1(n33[2]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324_add_4_3.INIT0 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_3.INIT1 = 16'hfaaa;
    defparam r_sample_cnt_324_add_4_3.INJECT1_0 = "NO";
    defparam r_sample_cnt_324_add_4_3.INJECT1_1 = "NO";
    CCU2D r_sample_cnt_324_add_4_1 (.A0(GND_net), .B0(GND_net), .C0(GND_net), 
          .D0(GND_net), .A1(r_sample_cnt[0]), .B1(GND_net), .C1(GND_net), 
          .D1(GND_net), .COUT(n3000), .S1(n33[0]));   // f:/home/mini-step-fpga/prj/template/debug_core.v(172[37:56])
    defparam r_sample_cnt_324_add_4_1.INIT0 = 16'hF000;
    defparam r_sample_cnt_324_add_4_1.INIT1 = 16'h0555;
    defparam r_sample_cnt_324_add_4_1.INJECT1_0 = "NO";
    defparam r_sample_cnt_324_add_4_1.INJECT1_1 = "NO";
    LUT4 r_uart_rx_falling_I_8_2_lut (.A(rx_c), .B(r_uart_rx_buf), .Z(r_uart_rx_falling_N_527)) /* synthesis lut_function=(!(A+!(B))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(92[25:46])
    defparam r_uart_rx_falling_I_8_2_lut.init = 16'h4444;
    LUT4 i2970_4_lut (.A(n9), .B(n3423), .C(n736[2]), .D(r_sample_cnt[5]), 
         .Z(clk_c_enable_159)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ;
    defparam i2970_4_lut.init = 16'hfdff;
    LUT4 i3_4_lut (.A(r_sample_cnt[6]), .B(n736[0]), .C(r_sample_cnt[3]), 
         .D(r_sample_cnt[4]), .Z(n9)) /* synthesis lut_function=(A (B (C+(D)))) */ ;
    defparam i3_4_lut.init = 16'h8880;
    LUT4 i1_2_lut_3_lut (.A(n736[0]), .B(n736[2]), .C(n736[1]), .Z(clk_c_enable_22)) /* synthesis lut_function=((B+(C))+!A) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(168[18] 180[16])
    defparam i1_2_lut_3_lut.init = 16'hfdfd;
    
endmodule
//
// Verilog Description of module Debug_core_DecodeUart
//

module Debug_core_DecodeUart (cnt, n3707, cmd_data, clk_c, rx_data, 
            cmd, rst_n, n3702, valid_o, clk_c_enable_102, \cnt[1] , 
            \cnt_2__N_615[1] , n3971, \cnt_2__N_615[0] ) /* synthesis syn_module_defined=1 */ ;
    output [2:0]cnt;
    input n3707;
    output [31:0]cmd_data;
    input clk_c;
    input [7:0]rx_data;
    output [7:0]cmd;
    input rst_n;
    output n3702;
    output valid_o;
    output clk_c_enable_102;
    output \cnt[1] ;
    input \cnt_2__N_615[1] ;
    input n3971;
    input \cnt_2__N_615[0] ;
    
    wire clk_c /* synthesis SET_AS_NETWORK=clk_c, is_clock=1 */ ;   // f:/home/mini-step-fpga/prj/template/top.v(3[8:11])
    
    wire n3374, n3697, clk_c_enable_43, clk_c_enable_32, clk_c_enable_71, 
        clk_c_enable_62, cst, clk_c_enable_52, n3356;
    wire [2:0]cnt_c;   // f:/home/mini-step-fpga/prj/template/debug_core.v(372[11:14])
    
    wire n1807;
    wire [2:0]cnt_2__N_615;
    
    wire clk_c_enable_144, n3337, n8, n7, n3343, n3445, n12;
    wire [31:0]nst_N_625;
    
    wire n13, n3429;
    
    LUT4 i2_4_lut (.A(n3374), .B(cnt[0]), .C(n3697), .D(n3707), .Z(clk_c_enable_43)) /* synthesis lut_function=(A (B (C (D)))) */ ;
    defparam i2_4_lut.init = 16'h8000;
    FD1P3AX data_i31 (.D(rx_data[7]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[31])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i31.GSR = "ENABLED";
    FD1P3AX data_i30 (.D(rx_data[6]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[30])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i30.GSR = "ENABLED";
    FD1P3AX data_i29 (.D(rx_data[5]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[29])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i29.GSR = "ENABLED";
    FD1P3AX data_i28 (.D(rx_data[4]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[28])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i28.GSR = "ENABLED";
    FD1P3AX data_i27 (.D(rx_data[3]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[27])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i27.GSR = "ENABLED";
    FD1P3AX data_i26 (.D(rx_data[2]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[26])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i26.GSR = "ENABLED";
    FD1P3AX data_i25 (.D(rx_data[1]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[25])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i25.GSR = "ENABLED";
    FD1P3AX data_i24 (.D(rx_data[0]), .SP(clk_c_enable_32), .CK(clk_c), 
            .Q(cmd_data[24])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i24.GSR = "ENABLED";
    FD1P3AX cmd_i0 (.D(rx_data[0]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i0.GSR = "ENABLED";
    FD1P3AX data_i0 (.D(rx_data[0]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i0.GSR = "ENABLED";
    FD1S3AX cst_70 (.D(n3697), .CK(clk_c), .Q(cst)) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(379[9:21])
    defparam cst_70.GSR = "ENABLED";
    FD1P3AX data_i23 (.D(rx_data[7]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[23])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i23.GSR = "ENABLED";
    FD1P3AX data_i22 (.D(rx_data[6]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[22])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i22.GSR = "ENABLED";
    FD1P3AX data_i21 (.D(rx_data[5]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[21])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i21.GSR = "ENABLED";
    FD1P3AX data_i20 (.D(rx_data[4]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[20])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i20.GSR = "ENABLED";
    LUT4 rst_n_I_0_1_lut_rep_53 (.A(rst_n), .Z(n3702)) /* synthesis lut_function=(!(A)) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(48[8:14])
    defparam rst_n_I_0_1_lut_rep_53.init = 16'h5555;
    FD1P3AX data_i19 (.D(rx_data[3]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[19])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i19.GSR = "ENABLED";
    FD1P3AX data_i18 (.D(rx_data[2]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[18])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i18.GSR = "ENABLED";
    FD1P3AX data_i17 (.D(rx_data[1]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[17])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i17.GSR = "ENABLED";
    FD1P3AX data_i16 (.D(rx_data[0]), .SP(clk_c_enable_43), .CK(clk_c), 
            .Q(cmd_data[16])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i16.GSR = "ENABLED";
    FD1P3AX data_i15 (.D(rx_data[7]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[15])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i15.GSR = "ENABLED";
    LUT4 i328_2_lut_2_lut (.A(rst_n), .B(valid_o), .Z(clk_c_enable_102)) /* synthesis lut_function=((B)+!A) */ ;   // f:/home/mini-step-fpga/prj/template/ledstatus.v(48[8:14])
    defparam i328_2_lut_2_lut.init = 16'hdddd;
    FD1P3AX data_i14 (.D(rx_data[6]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[14])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i14.GSR = "ENABLED";
    FD1P3AX data_i13 (.D(rx_data[5]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[13])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i13.GSR = "ENABLED";
    FD1P3AX data_i12 (.D(rx_data[4]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[12])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i12.GSR = "ENABLED";
    FD1P3AX data_i11 (.D(rx_data[3]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[11])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i11.GSR = "ENABLED";
    FD1P3AX data_i10 (.D(rx_data[2]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[10])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i10.GSR = "ENABLED";
    FD1P3AX data_i9 (.D(rx_data[1]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[9])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i9.GSR = "ENABLED";
    FD1P3AX data_i8 (.D(rx_data[0]), .SP(clk_c_enable_52), .CK(clk_c), 
            .Q(cmd_data[8])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i8.GSR = "ENABLED";
    FD1P3AX data_i7 (.D(rx_data[7]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i7.GSR = "ENABLED";
    FD1P3AX data_i6 (.D(rx_data[6]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i6.GSR = "ENABLED";
    FD1P3AX data_i5 (.D(rx_data[5]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i5.GSR = "ENABLED";
    FD1P3AX data_i4 (.D(rx_data[4]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i4.GSR = "ENABLED";
    FD1P3AX data_i3 (.D(rx_data[3]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i3.GSR = "ENABLED";
    FD1P3AX data_i2 (.D(rx_data[2]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i2.GSR = "ENABLED";
    FD1P3AX data_i1 (.D(rx_data[1]), .SP(clk_c_enable_62), .CK(clk_c), 
            .Q(cmd_data[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam data_i1.GSR = "ENABLED";
    FD1P3AX cmd_i7 (.D(rx_data[7]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[7])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i7.GSR = "ENABLED";
    FD1P3AX cmd_i6 (.D(rx_data[6]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[6])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i6.GSR = "ENABLED";
    FD1P3AX cmd_i5 (.D(rx_data[5]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[5])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i5.GSR = "ENABLED";
    FD1P3AX cmd_i4 (.D(rx_data[4]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[4])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i4.GSR = "ENABLED";
    FD1P3AX cmd_i3 (.D(rx_data[3]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[3])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i3.GSR = "ENABLED";
    FD1P3AX cmd_i2 (.D(rx_data[2]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i2.GSR = "ENABLED";
    FD1P3AX cmd_i1 (.D(rx_data[1]), .SP(clk_c_enable_71), .CK(clk_c), 
            .Q(cmd[1])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cmd_i1.GSR = "ENABLED";
    LUT4 i2_3_lut (.A(n3356), .B(cnt[0]), .C(cnt_c[2]), .Z(clk_c_enable_52)) /* synthesis lut_function=(!((B+!(C))+!A)) */ ;
    defparam i2_3_lut.init = 16'h2020;
    FD1S3IX cnt_i2 (.D(cnt_2__N_615[2]), .CK(clk_c), .CD(n1807), .Q(cnt_c[2])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cnt_i2.GSR = "ENABLED";
    FD1S3IX cnt_i1 (.D(\cnt_2__N_615[1] ), .CK(clk_c), .CD(n1807), .Q(\cnt[1] )) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cnt_i1.GSR = "ENABLED";
    FD1P3IX valid_o_72 (.D(n3971), .SP(clk_c_enable_144), .CD(n1807), 
            .CK(clk_c), .Q(valid_o));   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam valid_o_72.GSR = "ENABLED";
    FD1S3IX cnt_i0 (.D(\cnt_2__N_615[0] ), .CK(clk_c), .CD(n1807), .Q(cnt[0])) /* synthesis LSE_LINE_FILE_ID=3, LSE_LCOL=23, LSE_RCOL=2, LSE_LLINE=494, LSE_RLINE=502 */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(399[10] 418[8])
    defparam cnt_i0.GSR = "ENABLED";
    LUT4 i19_3_lut_4_lut (.A(cnt_c[2]), .B(cnt[0]), .C(cst), .D(n3337), 
         .Z(n8)) /* synthesis lut_function=(!(A (B (C+!(D))+!B !(C+(D)))+!A !(C+(D)))) */ ;
    defparam i19_3_lut_4_lut.init = 16'h7f70;
    LUT4 i4_4_lut (.A(n7), .B(n3343), .C(cnt[0]), .D(\cnt[1] ), .Z(clk_c_enable_144)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(411[24:35])
    defparam i4_4_lut.init = 16'h0800;
    LUT4 i2_2_lut (.A(rx_data[4]), .B(rx_data[6]), .Z(n7)) /* synthesis lut_function=(A (B)) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(411[24:35])
    defparam i2_2_lut.init = 16'h8888;
    LUT4 i7_4_lut (.A(n3445), .B(rx_data[1]), .C(n12), .D(rx_data[2]), 
         .Z(n3343)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(411[24:35])
    defparam i7_4_lut.init = 16'h1000;
    LUT4 i2912_4_lut (.A(rx_data[3]), .B(rx_data[5]), .C(rx_data[7]), 
         .D(rx_data[0]), .Z(n3445)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ;
    defparam i2912_4_lut.init = 16'hfeff;
    LUT4 i4_4_lut_adj_14 (.A(cnt_c[2]), .B(cnt[0]), .C(cst), .D(n3707), 
         .Z(n12)) /* synthesis lut_function=(A (B+((D)+!C))) */ ;   // f:/home/mini-step-fpga/prj/template/debug_core.v(411[24:35])
    defparam i4_4_lut_adj_14.init = 16'haa8a;
    LUT4 i2081_2_lut_3_lut (.A(cnt_c[2]), .B(cnt[0]), .C(\cnt[1] ), .Z(nst_N_625[0])) /* synthesis lut_function=(!(A (B (C)))) */ ;
    defparam i2081_2_lut_3_lut.init = 16'h7f7f;
    LUT4 i3_4_lut (.A(cnt[0]), .B(n8), .C(n3707), .D(n3374), .Z(clk_c_enable_32)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i3_4_lut.init = 16'h4000;
    LUT4 i7_4_lut_adj_15 (.A(n13), .B(rx_data[3]), .C(n3429), .D(rx_data[6]), 
         .Z(n3337)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
    defparam i7_4_lut_adj_15.init = 16'h0008;
    LUT4 i5_4_lut (.A(rx_data[4]), .B(rx_data[1]), .C(rx_data[5]), .D(rx_data[7]), 
         .Z(n13)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ;
    defparam i5_4_lut.init = 16'h4000;
    LUT4 i2896_2_lut (.A(rx_data[0]), .B(rx_data[2]), .Z(n3429)) /* synthesis lut_function=(A+(B)) */ ;
    defparam i2896_2_lut.init = 16'heeee;
    LUT4 rx_valid_bdd_4_lut_rep_48 (.A(n3707), .B(n3337), .C(nst_N_625[0]), 
         .D(cst), .Z(n3697)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C (D))) */ ;
    defparam rx_valid_bdd_4_lut_rep_48.init = 16'hf088;
    LUT4 i1_2_lut_3_lut (.A(cnt_c[2]), .B(cnt[0]), .C(n3356), .Z(clk_c_enable_62)) /* synthesis lut_function=(A (B (C))) */ ;
    defparam i1_2_lut_3_lut.init = 16'h8080;
    LUT4 i1307_1_lut_4_lut (.A(n3707), .B(n3337), .C(nst_N_625[0]), .D(cst), 
         .Z(n1807)) /* synthesis lut_function=(!(A (B (C+!(D))+!B (C (D)))+!A (C (D)))) */ ;
    defparam i1307_1_lut_4_lut.init = 16'h0f77;
    LUT4 i1_2_lut (.A(\cnt[1] ), .B(cnt_c[2]), .Z(n3374)) /* synthesis lut_function=(!((B)+!A)) */ ;
    defparam i1_2_lut.init = 16'h2222;
    LUT4 i2_3_lut_adj_16 (.A(n3356), .B(cnt[0]), .C(cnt_c[2]), .Z(clk_c_enable_71)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
    defparam i2_3_lut_adj_16.init = 16'h0808;
    LUT4 i2_4_lut_adj_17 (.A(cst), .B(n3707), .C(n3337), .D(\cnt[1] ), 
         .Z(n3356)) /* synthesis lut_function=(!(A ((D)+!B)+!A (((D)+!C)+!B))) */ ;
    defparam i2_4_lut_adj_17.init = 16'h00c8;
    LUT4 i387_3_lut_4_lut (.A(cnt[0]), .B(n3707), .C(\cnt[1] ), .D(cnt_c[2]), 
         .Z(cnt_2__N_615[2])) /* synthesis lut_function=(!(A (B (C (D)+!C !(D))+!B !(D))+!A !(D))) */ ;
    defparam i387_3_lut_4_lut.init = 16'h7f80;
    
endmodule
